US4063267A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MNOS Memory device
Assignee: McDonnell Douglas Corp
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Filing: 1976-06-21
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Granted: 1977-12-13
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Expires: 1996-06-21
Abstract
Abstract A method for fabricating a variable threshold IGFET free of parasitic effects and the "floating gate" effect. The IGFET includes an oxide layer having a portion of minimum thickness in the region thereof overlying an interstitial portion of a semiconductive substrate having a pair of spaced semiconductive diffusion regions, a portion of intermediate thickness partially overlying at least one of the pair of diffusion regions and the interstitial substrate portion, and a remaining portion of maximum thickness. The oxide layer portion of minimum thickness has a width greater than the width of an overlying electrically conductive gate electrode; the oxide layer portion of intermediate thickness has a width less than the width of the overlying electrode.
Inventors
- 👤 Yukun Hsia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0413; H10D30/60; H10D30/69
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
217 words
An insulative gate field effect transistor comprising: a semiconductive substrate of a first conductivity type; a pair of spaced semiconductive diffusion regions of opposite conductivity type to said substrate formed in said substrate, said diffusion regions being separated by an interstitial portion of said substrate and sharing a common boundary surface therewith; a layer of oxide material adhered to said common boundary surface, said layer having a portion of minimum thickness in the region thereof overlying said interstitial portion of said substrate, a portion of intermediate thickness partially overlying at least one of said pair of diffusion regions and said interstitial portion of said substrate, and a remaining portion of maximum thickness; a layer of dielectric material adhered to said oxide layer; and an electrically conductive electrode of predetermined width adhered to said dielectric layer in the region overlying said interstitial substrate portion; said oxide layer portion of minimum thickness having a width greater than the width of said electrically conductive electrode to define with the overlying portion of said dielectric layer and the underlying portion of said semiconductive substrate an insulative gate region; said oxide layer portion of intermediate thickness having a width less than the width of said electrically conductive electrode to define with the underlying portion of said semiconductive substrate an MOS gate region.
Claim 2
Dependent Claim
217 words
An insulative gate field effect transistor comprising: a semiconductive substrate of a first conductivity type; a pair of spaced semiconductive diffusion regions of opposite conductivity type to said substrate formed in said substrate, said diffusion regions being separated by an interstitial portion of said substrate and sharing a common boundary surface therewith; a layer of oxide material adhered to said common boundary surface, said layer having a portion of minimum thickness in the region thereof overlying said interstitial portion of said substrate, a portion of intermediate thickness partially overlying at least one of said pair of diffusion regions and said interstitial portion of said substrate, and a remaining portion of maximum thickness; a layer of dielectric material adhered to said oxide layer; and an electrically conductive electrode of predetermined width adhered to said dielectric layer in the region overlying said interstitial substrate portion; said oxide layer portion of minimum thickness having a width greater than the width of said electrically conductive electrode to define with the overlying portion of said dielectric layer and the underlying portion of said semiconductive substrate an insulative gate region; said oxide layer portion of intermediate thickness having a width less than the width of said electrically conductive electrode to define with the underlying portion of said semiconductive substrate an MOS gate region.
Claim 3
Dependent Claim
37 words
The combination of claim 1 wherein said oxide layer portion of intermediate thickness extends in opposite directions from said interstitial substrate portion and partially overlies both of said pair of diffusion regions and said interstitial substrate portion.
Claim 4
Dependent Claim
19 words
The combination of claim 1 wherein said first and said opposite conductivity types are N and P types, respectively.
Claim 5
Dependent Claim
12 words
The combination of claim 1 wherein said oxide material comprises silicon dioxide.
Claim 6
Dependent Claim
16 words
The combination of claim 1 wherein said minimum thickness of said oxide layer is about 20A.
Claim 7
Dependent Claim
24 words
The combination of claim 1 wherein said minimum thickness of said oxide layer is in the range from 10A to about several hundred A.
Claim 8
Dependent Claim
16 words
The combination of claim 1 wherein said intermediate thickness of said oxide layer is about 1400A.
Claim 9
Dependent Claim
12 words
The combination of claim 1 wherein said dielectric material comprises silicon nitride.
Claim 10
Dependent Claim
21 words
The combination of claim 1 wherein said dielectric layer has a thickness in the range from about 400A to about 800A.
Claim 11
Dependent Claim
16 words
The combination of claim 1 wherein said dielectric layer has a thickness of about 650A units.
Claim 12
Dependent Claim
36 words
The combination of claim 1 wherein the width of said oxide layer portion of minimum thickness is greater than the width of said electrically conductive electrode by one minimum alignment tolerance length on each side thereof.
Claim 13
Dependent Claim
15 words
The combination of claim 11 wherein said minimum alignment tolerance length is about four microns.
Claim 14
Dependent Claim
33 words
The combinations of claim 1 wherein said oxide layer portion of minimum thickness is no closer to said at least one of said pair of diffusion regions than one minimum alignment tolerance length.
Claim 15
Dependent Claim
15 words
The combination of claim 13 wherein said minimum alignment tolerance length is about four microns.
Claim 16
Dependent Claim
33 words
The combination of claim 1 wherein said oxide layer portion of intermediate thickness is smaller than the width of said electrically conductive electrode by one minimum alignment tolerance length on each side thereof.
Claim 17
Dependent Claim
15 words
The combination of claim 15 wherein said minimum alignment tolerance length is about four microns.
References Cited (Backward Citations)
US3846768A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-12 | 1981-06-13 | 1981-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-12 | 1985-06-13 | 1985-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-12 | 1989-06-13 | 1989-12-13 | $7700.00 | Window Closed / Lapsed |