US4609833A
Expired / Lapsed
US
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Simple NMOS voltage reference circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1983-08-12
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Granted: 1986-09-02
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Expires: 2003-08-12
Abstract
Abstract A simple, compact voltage reference circuit for an NMOS integrated circuit comprises a series connected depletion transistor with its gate at ground and an enhancement transistor with its gate connected to an output node between the two transistors.
Inventors
- 👤 Daniel C. Guterman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:27
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/245; G05F3/247
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
121 words
A voltage reference circuit for an NMOS integrated circuit comprising: a semiconductor substrate; a self-based enhancement transistor, formed in said substrate, and connected between ground and an output node, having and enhancement gate, with an enhancement gate width and enhancement gate length, connected to said output node; and a self-biased depletion transistor, formed in said substrate, and connected between said output node and a supply voltage terminal, having a depletion gate, with a depletion gate width and a depletion gate length, connected to ground; said enhancement transistor and said depletion transistor are substantially matched in size, whereby the ratio of a width to length ratio of said enhancement transistor and a width to length ratio of said depletion transistor is one.
Claim 2
Dependent Claim
121 words
A voltage reference circuit for an NMOS integrated circuit comprising: a semiconductor substrate; a self-based enhancement transistor, formed in said substrate, and connected between ground and an output node, having and enhancement gate, with an enhancement gate width and enhancement gate length, connected to said output node; and a self-biased depletion transistor, formed in said substrate, and connected between said output node and a supply voltage terminal, having a depletion gate, with a depletion gate width and a depletion gate length, connected to ground; said enhancement transistor and said depletion transistor are substantially matched in size, whereby the ratio of a width to length ratio of said enhancement transistor and a width to length ratio of said depletion transistor is one.
Claim 3
Dependent Claim
48 words
A voltage reference circuit according to claim 1, in which said depletion transistor is formed by a depletion dose of substantially 1×10 12 ions/cm 2 together with an enhancement dose of between 1 and 4×10 11 /cm 2 and said enhancement transistor is formed by said enhancement dose.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |