US4471290A
Expired / Lapsed
US
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Substrate bias generating circuit
Assignee: Toshiba Corp
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Filing: 1982-05-26
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Granted: 1984-09-11
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Expires: 2002-05-26
Abstract
Abstract A substrate bias generating circuit includes an oscillator circuit having a control terminal and a bias generating circuit for generating a negative substrate bias voltage responsive to the output signal of the oscillator circuit. The substrate bias generating circuit further includes a voltage divider connected between the output terminal of the bias generating circuit and a ground terminal, and a level sensor for producing a control signal to the oscillator circuit when it is detected that the output voltage of the voltage divider reaches a predetermined value, to thereby stop the oscillating operation of the oscillator circuit.
Inventors
- 👤 Kazuo Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:26
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C5/146; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; Y; Y10; Y10S; Y10S331/00; Y10S331/03
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
174 words
A substrate bias generating circuit comprising reference potential means and oscillator means having a control terminal; bias generating means for generating a substrate bias voltage at a first output terminal in response to the output signal of said oscillator means; voltage generating means connected between said first output terminal and said reference potential means to generate at a second output terminal an output voltage having an absolute value not higher than the absolute value of the substrate bias voltage from said bias generating means and varying in a predetermined relationship with respect to said substrate bias voltage; and control means including depletion-type MOS transistor means connected at the gate thereof to said second output terminal and first resistance means connected in series with the current path of said depletion-type MOS transistor means for controlling the oscillating operation of said oscillator means by applying a control signal to said oscillator control terminal when the output voltage of said voltage generating means reaches a level determined by the voltage threshold of said depletion-type MOS transistor means.
Claim 2
Dependent Claim
174 words
A substrate bias generating circuit comprising reference potential means and oscillator means having a control terminal; bias generating means for generating a substrate bias voltage at a first output terminal in response to the output signal of said oscillator means; voltage generating means connected between said first output terminal and said reference potential means to generate at a second output terminal an output voltage having an absolute value not higher than the absolute value of the substrate bias voltage from said bias generating means and varying in a predetermined relationship with respect to said substrate bias voltage; and control means including depletion-type MOS transistor means connected at the gate thereof to said second output terminal and first resistance means connected in series with the current path of said depletion-type MOS transistor means for controlling the oscillating operation of said oscillator means by applying a control signal to said oscillator control terminal when the output voltage of said voltage generating means reaches a level determined by the voltage threshold of said depletion-type MOS transistor means.
Claim 3
Dependent Claim
47 words
A substrate bias generating circuit according to claim 1, wherein said voltage generating means includes a voltage divider having resistance means connected in series between said first output terminal and said reference potential means and generating an output voltage determined by the value of said resistance means.
Claim 4
Dependent Claim
36 words
A substrate bias generating circuit according to claim 1, wherein said control means further includes inverter circuit means having an input connected to the junction between said depletion-type MOS transistor means and said first resistance means.
Claim 5
Dependent Claim
20 words
A substrate bias generating circuit according to claim 3, wherein said inverter circuit means includes a plurality of series-connected inverters.
Claim 6
Dependent Claim
22 words
A substrate bias generating circuit according to claim 4, wherein at least one of said plurality of series-connected inverters has hysteresis characteristics.
Claim 7
Dependent Claim
77 words
A substrate bias generating circuit according to claim 1, wherein said voltge generating means is a difference voltage generating circuit connected between the first output terminal of said bias generating means and the reference potential means for generating a difference voltage between the output voltage of said bias generating means and a predetermined voltage when the absolute value of the output voltage of said bias generating means is larger than the absolute value of the predetermined voltage.
Claim 8
Dependent Claim
89 words
A substrate bias generating circuit according to claim 6, wherein said difference voltage generating circuit includes a plurality of series-connected circuit units, said circuit units each having resistive means and voltage drop means for generating a predetermined voltage drop, said voltage drop means being connected at one end to said reference potential means and at the other end to the first output terminal of said bias generating means through said resistive means for generating an output voltage from the junction between the resistive means and the voltage drop means.
Claim 9
Dependent Claim
34 words
A substrate bias generating circuit according to claim 7, wherein said voltage drop means has a depletion type MOS transistor connected at the gate thereof to the output terminal of said bias generating means.
Claim 10
Dependent Claim
85 words
A substrate bias generating circuit according to claim 6, wherein said difference voltage generating circuit includes resistance means connected at one end thereof to the first output terminal of said bias generating means, and voltage drop means, connected at one end thereof to said reference potential means and connected at the other end thereof to the other end of said resistance means, for generating a predetermined voltage drop, and generates an output voltage from the junction between said resistive means and said voltage drop means.
Claim 11
Dependent Claim
35 words
A substrate bias generating circuit according to claim 9, wherein said voltage drop means has a depletion type MOS transistor connected at the gate thereof to the first output terminal of said bias generating means.
Claim 12
Dependent Claim
84 words
A substrate bias generating circuit according to claim 6, wherein said differential voltage generating means includes resistance means connected at one end thereof to the reference potential means, and voltage drop means, connected at one end thereof to the first output terminal of said bias generating means and at the other end thereof to the other end of said resistance means, for generating a predetermined voltage drop, and generates an output voltage from the junction between the resistance means and the voltage drop means.
Claim 13
Dependent Claim
87 words
Integrated circuit substrate bias generating means comprising: selectively operable charge pumping means connected to said substrate for changing the voltage bias level thereof; control means for generating a control signal by comparing the voltage threshold level of a MOS transistor with a portion of said substrate voltage bias level; and means coupling said control signal to said charge pumping means to control the operation thereof, whereby said substrate bias is maintained at a level substantially equal to a constant multiple of said MOS transistor voltage threshold level.
Claim 14
Dependent Claim
87 words
Integrated circuit substrate bias generating means comprising: selectively operable charge pumping means connected to said substrate for changing the voltage bias level thereof; control means for generating a control signal by comparing the voltage threshold level of a MOS transistor with a portion of said substrate voltage bias level; and means coupling said control signal to said charge pumping means to control the operation thereof, whereby said substrate bias is maintained at a level substantially equal to a constant multiple of said MOS transistor voltage threshold level.
References Cited (Backward Citations)
US3806741A
Cited
JPS5024054A
Cited
US4142114A
Cited
DE2812378A1
Cited
US4266151A
Cited
US4388537A
Cited
US4322675A
Cited
US4344121A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-11 | 1988-03-12 | 1988-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-11 | 1992-03-12 | 1992-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-11 | 1996-03-12 | 1996-09-11 | $7700.00 | Window Closed / Lapsed |