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US4603468A
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Method for source/drain self-alignment in stacked CMOS
Assignee: Texas Instruments Inc
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Filing: 1984-09-28
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Granted: 1986-08-05
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Expires: 2004-09-28
Abstract
Abstract In stacked CMOS, a single gate in first level polycrystalline silicon is used to address both an N-channel device in the substrate and an overlaid p-channel device. The p-channel device has self-aligned source and drain regions formed by diffusing a dopant from doped regions underlying them. The doped regions are formed by planarizing a doped insulating layer, and etching the doped layer back to the upper level of the gate prior to deposition of a second polysilicon layer.
Inventors
- 👤 Hon W. Lam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:24
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/164
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
142 words
A process for fabricating a self-aligned stacked CMOS structure, comprising the steps of: (a) fabricating source and drain regions having a first conductivity type in a substrate having a second conductivity type; (b) fabricating a gate region on the surface of the substrate having a sidewall oxide; (c) forming a first insulating layer containing a dopant of the second conductivity type on the surface of said substrate with an upper surface of the gate region exposed; (d) forming a second insulating layer over said exposed surface of said gate; (e) forming a polycrystalline silicon layer over the first and second insulating layers; and (f) causing dopant from the first insulating layer to diffuse into the polycrystalline layer thereover to form heavily doped upper source and drain regions in the polycrystalline silicon, the portion of the polycrystalline layer therebetween being relatively lightly doped.
Claim 2
Dependent Claim
142 words
A process for fabricating a self-aligned stacked CMOS structure, comprising the steps of: (a) fabricating source and drain regions having a first conductivity type in a substrate having a second conductivity type; (b) fabricating a gate region on the surface of the substrate having a sidewall oxide; (c) forming a first insulating layer containing a dopant of the second conductivity type on the surface of said substrate with an upper surface of the gate region exposed; (d) forming a second insulating layer over said exposed surface of said gate; (e) forming a polycrystalline silicon layer over the first and second insulating layers; and (f) causing dopant from the first insulating layer to diffuse into the polycrystalline layer thereover to form heavily doped upper source and drain regions in the polycrystalline silicon, the portion of the polycrystalline layer therebetween being relatively lightly doped.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type.
Claim 4
Dependent Claim
12 words
The method of claim 2, wherein the insulating layer dopant is boron.
Claim 5
Dependent Claim
19 words
The method of claim 1, wherein the first conductivity type is p-type, and the second conductivity type is n-type.
Claim 6
Dependent Claim
14 words
The method of claim 4, wherein the insulating layer dopant is phosphorus or arsenic.
Claim 7
Dependent Claim
52 words
The method of claim 1, wherein step (c) comprises the steps of: (f) forming an insulating layer over the source, drain, and gate regions; (g) etching the insulating layer until an upper surface of the gate region is exposed; and (h) forming a gate oxide on the exposed gate region upper surface.
Claim 8
Dependent Claim
74 words
The method of claim 1, wherein step (c) comprises the steps of: (i) forming an insulating layer over the source, drain, and gate regions; (j) forming a planarization layer over the insulating layer; (k) etching the planarization layer and the insulating layer until an upper surface of the gate region is exposed; (l) removing all remaining portions of the planarization layer; and (m) forming a gate oxide on the exposed gate region upper surface.
Claim 9
Independent Claim
15 words
The method of claims 6 or 7, wherein the insulating layer comprises boron-doped silicate glass.
Claim 10
Independent Claim
21 words
The method of claims 6 or 7, wherein the insulating layer comprises phosphorus doped silicate glass or arsenic doped silicate glass.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |