Patent US4603301A successfully refreshed from Google Patents.
US4603301A
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Amplitude insensitive delay lines in a frequency modulated signal detector
Assignee: Agilent Technologies Inc
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Filing: 1984-07-05
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Granted: 1986-07-29
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Expires: 2004-07-05
Abstract
Abstract A circuit for detecting a Frequency Modulated (FM) signal is provided. An amplitude limited FM signal is propated through a delay circuit comprising a plurality of cascaded saturating inverters. A Boolean logic "Exclusive Or" (XOR) operation is performed between the FM signal before entering the delay circuit and after exiting the delay circuit.
Inventors
- 👤 John N. Dukes
- 👤 Richard A. Baumgartner
- 👤 Thomas A. Shoup
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:46
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
111 words
A circuit for detecting an FM signal comprising: a plurality of cascaded saturating circuit elements having and having an input on which is applied the FM signal, and output on which the plurality of cascaded saturating circuit elements couples a first delay signal, and each saturating circuit element having a control means for varying delay of the applied FM signal through that saturating circuit element; and, combining means coupled to the output of the plurality of cascaded saturating circuit elements for producing a second delay signal and varying a duty cycle of the second delay signal based on the relative phase difference between the FM signal and the first delay signal.
Claim 2
Dependent Claim
111 words
A circuit for detecting an FM signal comprising: a plurality of cascaded saturating circuit elements having and having an input on which is applied the FM signal, and output on which the plurality of cascaded saturating circuit elements couples a first delay signal, and each saturating circuit element having a control means for varying delay of the applied FM signal through that saturating circuit element; and, combining means coupled to the output of the plurality of cascaded saturating circuit elements for producing a second delay signal and varying a duty cycle of the second delay signal based on the relative phase difference between the FM signal and the first delay signal.
Claim 3
Dependent Claim
62 words
A circuit as in claim 1 additionally comprising: low pass filter means coupled to the combining means for filtering the second delay signal; and feedback means coupled to the plurality of cascaded saturating circuit elements and coupled to the low pass filter means for assuring that the plurality of cascaded saturating circuit elements performs an odd multiple of a 90° phase shift.
Claim 4
Dependent Claim
54 words
A circuit as in claim 1 wherein each cascaded saturating circuit element includes an inverter; and, each control means comprises a first node coupled to a voltage source, a second node coupled to the inverter and a third node on which may be placed a signal in order to vary delay through the inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-28 | 1990-01-27 | 1990-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-28 | 1994-01-27 | 1994-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-28 | 1998-01-27 | 1998-07-29 | $7700.00 | Window Closed / Lapsed |