Patent US4593203A successfully refreshed from Google Patents.
US4593203A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit which allows adjustment of circuit characteristics in accordance with storage data of nonvolatile memory element
Assignee: Toshiba Corp
•
Filing: 1983-02-08
•
Granted: 1986-06-03
•
Expires: 2003-02-08
Abstract
Abstract The invention provides a semiconductor integrated circuit, characteristics of which can be adjusted in accordance with storage data in a nonvolatile memory element. The semiconductor integrated circuit has a main semiconductor circuit having MOS transistors, and an adjusting circuit connected to the main semiconductor circuit so as to change the circuit characteristics of the main semiconductor circuit as needed. The adjusting circuit has MOS transistors and a plurality of fuse elements. The adjusting circuit causes a given fuse element to selectively disconnect in accordance with an input signal and generates at least one adjusting signal to adjust the circuit characteristics of the main semiconductor circuit.
Inventors
- 👤 Hiroshi Iwahashi
- 👤 Masamichi Asano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:35
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/354; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C7/00; G11C7/14; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; G11C7/06
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
107 words
A semiconductor integrated circuit, comprising: a main semiconductor circuit having a plurality of MOS transistors of a first group arranged to perform a function at an operating speed and current consumption which is responsive to an adjusting signal; and circuit means for generating said adjusting signal to permanently set said main semiconductor circuit at a desired operating speed and current consumption, said circuit means including a plurality of MOS transistors of a second group and a fuse coupled together to produce said adjusting signal and to permanently alter said adjusting signal upon opening of said fuse, said circuit means further including means for selectively opening said fuse.
Claim 2
Dependent Claim
107 words
A semiconductor integrated circuit, comprising: a main semiconductor circuit having a plurality of MOS transistors of a first group arranged to perform a function at an operating speed and current consumption which is responsive to an adjusting signal; and circuit means for generating said adjusting signal to permanently set said main semiconductor circuit at a desired operating speed and current consumption, said circuit means including a plurality of MOS transistors of a second group and a fuse coupled together to produce said adjusting signal and to permanently alter said adjusting signal upon opening of said fuse, said circuit means further including means for selectively opening said fuse.
Claim 3
Dependent Claim
100 words
A circuit according to claim 1 wherein one of said MOS transistors of said first group has a gate coupled to receive said adjusting signal and said main semiconductor circuit comprises an inverter circuit of said MOS transistors having source-drain paths which are connected in series with each other, one end of a series arrangement of said source-drain paths being connected to a first reference power supply, and the other end thereof being connected to a second reference power supply through said one of said MOS transistors of said first group which receives the adjusting signal at a gate thereof.
Claim 4
Dependent Claim
31 words
A circuit according to claim 2, wherein said one of said MOS transistors of said first group which receives the adjusting signal at said gate thereof is of an enhancement type.
Claim 5
Dependent Claim
31 words
A circuit according to claim 2, wherein said one of said MOS transistors of said first group which receives the adjusting signal at said gate thereof is of a depletion type.
Claim 6
Dependent Claim
118 words
A semiconductor integrated circuit, comprising: a main semiconductor circuit having a plurality of MOS transistors of a first group arranged to perform a function at an operating speed and current consumption which is responsive to a plurality of adjusting signals; and circuit means for generating said plurality of adjusting signals to permanently set said main semiconductor circuit at a desired operating speed and current consumption, said circuit means including a plurality of MOS transistors of a second group and a plurality of fuses coupled to said plurality of MOS transistors to produce said adjusting signals and to permanently alter said adjusting signals upon opening of said fuses, said circuit means further including means for selectively opening said fuses.
Claim 7
Dependent Claim
118 words
A semiconductor integrated circuit, comprising: a main semiconductor circuit having a plurality of MOS transistors of a first group arranged to perform a function at an operating speed and current consumption which is responsive to a plurality of adjusting signals; and circuit means for generating said plurality of adjusting signals to permanently set said main semiconductor circuit at a desired operating speed and current consumption, said circuit means including a plurality of MOS transistors of a second group and a plurality of fuses coupled to said plurality of MOS transistors to produce said adjusting signals and to permanently alter said adjusting signals upon opening of said fuses, said circuit means further including means for selectively opening said fuses.
Claim 8
Dependent Claim
175 words
A circuit according to claim 5, wherein said main semiconductor circuit comprises an inverter circuit of a CMOS structure having first and second MOS transistors of said first group, said first MOS transistor having a source-drain path, one end of which is connected to a first reference power supply through a third MOS transistor of said first group, said third MOS transistor being coupled to receive one of said adjusting signals at a gate thereof, and the other end of which is connected to one end of a source-drain path of said second MOS transistor the other end of which is connected to a second reference power supply through a source-drain path of a fourth MOS transistor of said first group, said fourth MOS transistor being coupled to receive another of said adjusting signals at a gate thereof, said third MOS transistor having the same conductivity type as a conductivity type of said first MOS transistor, and said fourth MOS transistor having the same conductivity type as a conductivity type of said second MOS transistor.
Claim 9
Dependent Claim
151 words
A circuit according to claim 6, further comprising: a fifth MOS transistor of said first group, a source-drain path of which is connected between said one end of the source-drain path of said first MOS transistor and said first reference power supply, said fifth MOS transistor having the same conductivity type as the conductivity type of said third MOS transistor and receiving, at a gate thereof, the same adjusting signal applied to said gate of said fourth MOS transistor; and a sixth MOS transistor of said first group, a source-drain path of which is connected between the other end of the source-drain path of said second MOS transistor and said second reference power supply, said sixth MOS transistor having the same conductivity type as the conductivity type of said fourth MOS transistor and receiving, at a gate thereof, the same adjusting signal applied to said gate of said third MOS transistor.
References Cited (Backward Citations)
US4084105A
Cited
US4424456A
Cited
US4464587A
Cited
US4446534A
Cited
US4499387A
Cited
US4417154A
Cited
US4476546A
Cited
US4481432A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |