Programmable output buffer

Claim 1

An output buffer circuit comprising: a first P channel MOS transistor having a drain connected to a first potential, a gate connected to an input control signal, and a source; a first N channel MOS transistor having a drain, a gate connected to said input control signal, and a source connected to a reference potential; an output node connected to said drain of said first N channel MOS transistor; a second N channel MOS transistor having a drain connected to said source of said first P channel MOS transistor, a source connected to said drain of said first N channel MOS transistor, and a gate connected to a programming terminal for receiving a programming voltage; wherein a low programming voltage causes said second N channel MOS transistor to turn off, and thus when said input control signal is high, said first P channel transistor is off, said first N channel transistor is on, said output node has a potential substantially equal to said reference potential, thus providing a logical zero output signal; and thus when said input control signal is low, said first N channel transistor is off, said second N channel transistor is off, and said output node is isolated from said first potential and from said reference potential; and wherein a high programming voltage causes said second N channel transistor to turn on, and thus, when said input control signal is high, said first N channel MOS transistor is on, said first P channel MOS transistor is off, and thus said output node is thereby connected to said reference potential thus providing a logical zero output signal; conversely, when said input control signal is low, said first N channel MOS transistor is off, said first P channel MOS transistor is on, thus said output node is thereby connected to said first potential, thus providing a logical one output signal.