Data output circuit with means for preventing more than half the output lines from transitioning simultaneously

Claim 2

A data output circuit comprising: data input terminals for receiving logic signals of input data; a latching means, connected to the data input terminals, to hold the logic signals of input data in accordance with a first control signal and the inverted replica of said logic signals in accordance with a second control signal; a control signal generating means for checking the coincidence between each of the logic signals of updated input data applied to the data input terminals and a corresponding one of the output signals of said latching means, and supplying the first control signal when it is detected that the number of the logic signals of said updated input data, which are same in logic level as their corresponding output signals of said latching means, is larger than a preset value, and also supplying the second control signal when it is detected that the number of the logic signals of said updated input data, which are same in logic level as their corresponding output signals of said latching means, is not larger than the preset value; a notation signal generating means for generating a logic notation signal, which represents the logic notation with respect to the output signals of said latching means, in accordance with an output signal applied from said control signal generating means; and output buffer means for supplying logic signals which correspond to the output signals of said latching means and the logic notation signal applied from the notation signal generating means.

Claim 3

A data output circuit according to claim 1, wherein said latching means includes a plurality of transferring circuits, connected to said data input terminals, to respectively supply the logic signals of said input data in response to the first control signal and the inverted replica of said logic signals in response to the second control signal, and a plurality of latching circuits for holding the respective output signals of said transferring circuits in response to a clock pulse.

Claim 4

A data output circuit according to claim 2, wherein said transferring circuits are exclusive OR gates.

Claim 5

A data output circuit according to claim 2, wherein said latching circuits are D-type flip-flops.

Claim 6

A data output circuit according to claim 2, wherein said output buffer means includes a plurality of first output buffers for supplying logic signals which correspond to the output signals of said latching circuits, and a second output buffer for supplying a logic signal which corresponds to the logic notation signal applied from said notation signal generating means.

Claim 7

A data output circuit according to claim 5, wherein said control signal generating means includes a plurality of comparators, each checking the coincidence between one of the logic signals of updated input data applied to said data input terminals and its corresponding one of the output signals of said latching means, and a detecting circuit for supplying one of the first and second control signals in accordance with the number of coincident signals applied from said comparators.

Claim 8

A data output circuit according to claim 6, wherein said comparators are exclusive OR gates whose first input terminals are connected to said data input terminals, and whose second input terminals are connected to their corresponding output terminals of said latching circuits.

Claim 9

A data output circuit according to claim 5, wherein said comparators are exclusive OR gates whose first input terminals are connected to said data input terminals, and whose second input terminals are connected to their corresponding output terminals of said first output buffers.

Claim 10

A data output circuit according to claim 7, wherein said detecting circuit is a majority circuit.

Claim 11

A data output circuit according to claim 7, wherein said notation signal generating means includes a D-type flip-flop for supplying a logic signal, which corresponds to the output signal of said control signal generating means, in response to the clock pulse.

Claim 12

A data output circuit comprising: data input terminals for respectively receiving logic signals of input data; a latching means, connected to the data input terminals, to hold the logic signals of input data in accordance with a first control signal and the inverted replica of said logic signals in accordance with a second control signal; a control signal generating means for checking the coincidence between each of the logic signals of updated input data applied to the data input terminals and its corresponding one of the output signals of said latching means, and supplying the first control signal when it is detected that the number of the logic signals of said updated input data, which are same in logic level as their corresponding output signals of said latching means, is larger than a preset value, and also supplying the second control signal when it is detected that the number of the logic signals of said updated input data, which are the same in logic level as their corresponding output signals of said latching means, is not larger than the preset value; a notation signal generating means for generating a logic notation signal, which represents the logic notation with respect to the output signals of said latching means, in accordance with an output signal applied from said control signal generating means; an output buffer means for supplying logic signals which correspond to the output signals of said latching means and the logic notation signal applied from the notation signal generating means; bus lines through which the output signals of said output buffer means are transferred; and a transferring means for supplying one of the logic signals from said bus lines and the inverted replica of said logic signal in accordance with the logic notation signal.

Claim 13

A data output circuit comprising: data input terminals for respectively receiving logic signals of input data; a latching means, connected to the data input terminals, to hold the logic signals of input data in accordance with a first control signal and the inverted replica of said logic signals in accordance with a second control signal; a control signal generating means for checking the coincidence between each of the logic signals of updated input data applied to the data input terminals and its corresponding one of the output signals of said latching means, and supplying the first control signal when it is detected that the number of the logic signals of said updated input data, which are same in logic level as their corresponding output signals of said latching means, is larger than a preset value, and also supplying the second control signal when it is detected that the number of the logic signals of said updated input data, which are the same in logic level as their corresponding output signals of said latching means, is not larger than the preset value; a notation signal generating means for generating a logic notation signal, which represents the logic notation with respect to the output signals of said latching means, in accordance with an output signal applied from said control signal generating means; an output buffer means for supplying logic signals which correspond to the output signals of said latching means and the logic notation signal applied from the notation signal generating means; bus lines through which the output signals of said output buffer means are transferred; and a transferring means for supplying one of the logic signals from said bus lines and the inverted replica of said logic signal in accordance with the logic notation signal.