US4481427A
Expired / Lapsed
US
⏱️ 0.0 years remaining
TTL Circuit having delay means for delaying the operation until the supply voltage reaches a certain threshold
Assignee: Fujitsu Ltd
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Filing: 1982-11-29
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Granted: 1984-11-06
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Expires: 2002-11-29
Abstract
Abstract A TTL circuit including an input circuit, an output circuit, elements for controlling the output circuit, and elements for delaying the operation of the controlling elements immediately after the voltage supply is turned on. The output of the TTL circuit is maintained at on "H" level until the voltage supply rises up to a predetermined level.
Inventors
- 👤 Hirokazu Suzuki
- 👤 Takehiro Akiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:23
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K2017/226
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
134 words
A transistor transistor logic (TTL) circuit operatively connected to receive an external TTL signal and having a voltage supply, comprising: an input circuit operatively connected to receive the external TTL signal, for producing an output signal; an output circuit operatively connected to said input circuit; means, operatively connected between said output circuit and said input circuit, for controlling said output circuit, said controlling means receiving the output signal from said input circuit and supplying a controlling signal to said output circuit; and means, included in said means for controlling said output circuit, for delaying the operation of said controlling means until the voltage supply rises to a predetermined level after turning on, whereby the output of said TTL circuit is maintained at a high level until the voltage supply rises to the predetermined level.
Claim 2
Dependent Claim
134 words
A transistor transistor logic (TTL) circuit operatively connected to receive an external TTL signal and having a voltage supply, comprising: an input circuit operatively connected to receive the external TTL signal, for producing an output signal; an output circuit operatively connected to said input circuit; means, operatively connected between said output circuit and said input circuit, for controlling said output circuit, said controlling means receiving the output signal from said input circuit and supplying a controlling signal to said output circuit; and means, included in said means for controlling said output circuit, for delaying the operation of said controlling means until the voltage supply rises to a predetermined level after turning on, whereby the output of said TTL circuit is maintained at a high level until the voltage supply rises to the predetermined level.
Claim 3
Dependent Claim
28 words
A TTL circuit as defined in claim 1, wherein said output circuit comprises first and second output transistors operatively connected in series between the voltage supply and ground.
Claim 4
Dependent Claim
64 words
A TTL circuit as defined in claim 1 or 2, wherein said means for controlling said output circuit comprises: a first resistor operatively connected to ground; a second resistor operatively connected to the voltage supply; and a phase-splitter transistor having an emitter operatively connected to said first resistor, having a collector operatively connected to said second resistor and having a base having a potential.
Claim 5
Dependent Claim
47 words
A TTL circuit as defined in claim 3, wherein said means for delaying the operation of said controlling means comprises level shift means operatively connected between the voltage supply and the base of said phase-splitter transistor, for controlling the potential of the base of said phase-splitter transistor.
Claim 6
Dependent Claim
22 words
A TTL circuit as defined in claim 4, wherein said level shift means comprises a plurality of diodes operatively connected in series.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-06 | 1988-05-07 | 1988-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-06 | 1992-05-07 | 1992-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-06 | 1996-05-07 | 1996-11-06 | $7700.00 | Window Closed / Lapsed |