EP0080874A2
Expired / Lapsed
EP
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Error prevention in TTL circuits
Assignee: Fujitsu Ltd
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Filing: 1982-11-26
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Granted: —
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Expires: 2002-11-26
Abstract
Abstract A TTL circuit, controllable by an input signal so that when the circuit is in a normal steady-state operating condition it delivers an output signal which will undergo a predetermined change in response to a predetermined change in the input signal, includes error prevention circuitry (DS 1 -DS n ) for preventing such response to said change in the input signal if a power supply voltage (Vcc) applied to the circuit is at a subnormal value, below a threshold value imposed by the error prevention circuitry, for example during start-up of the device.
Inventors
- 👤 Hirokazu Suzuki
- 👤 Takehiro Fujitsu Dai-1 Ichigao-Ryo Akiyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 02:55
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K2017/226
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
101 words
A TTL circuit comprising: an input circuit receiving an external TTL signal; an output circuit; means for controlling said output circuit, said controlling means receiving a signal from said input circuit and supplying a controlling signal to said output circuit; and means for delaying the operation of said controlling means until a voltage supply rises up to a predetermined level after the voltage supply is turned on, said delaying means inserted between said input circuit and said controlling means, whereby the output of said TTL circuit is maintained at high level until the voltage supply rises up to said predetermined level.
Claim 2
Dependent Claim
101 words
A TTL circuit comprising: an input circuit receiving an external TTL signal; an output circuit; means for controlling said output circuit, said controlling means receiving a signal from said input circuit and supplying a controlling signal to said output circuit; and means for delaying the operation of said controlling means until a voltage supply rises up to a predetermined level after the voltage supply is turned on, said delaying means inserted between said input circuit and said controlling means, whereby the output of said TTL circuit is maintained at high level until the voltage supply rises up to said predetermined level.
Claim 3
Dependent Claim
28 words
A TTL circuit as defined in claim 1, wherein said output circuit has first and second output transistors connected in series between the voltage supply and the ground.
Claim 4
Dependent Claim
53 words
A TTL circuit as defined in claim 1 or 2; wherein said means for controlling said output circuit has a phase--splitter transistor, an emitter of said phase splitter transistor being connected to the ground through a resistor, a collector of said phase splitter transistor being connected to the voltage supply through a resistor.
Claim 5
Dependent Claim
36 words
A TTL circuit as defined in claim 3; wherein said means for delaying the operation of said controlling means comprises a level shift means connected between the voltage supply and a base of said phase-splitter transistor.
Claim 6
Dependent Claim
21 words
A TTL circuit as defined in claim 4, wherein said level shift means comprises a plurality of diodes connected in series.
Claim 7
Dependent Claim
113 words
A TTL circuit controllable by an input signal so that when the circuit is in a normal steady-state operating condition it delivers an output signal which will unaergo a predetermined change in response to a predetermined change in the input signal, characterized by error prevention circuitry (US 1 - DSn) incorporated in the TTL circuit fur preventing such response to the said predetermined change in the input signal if a power supply voltage (Vcc) applied to the circuit is at a subnormal value, below a threshold value imposed by the said error prevention circuitry, at which subnormal value the said response could take place in the absence of the said error prevention circuitry.
Claim 8
Dependent Claim
113 words
A TTL circuit controllable by an input signal so that when the circuit is in a normal steady-state operating condition it delivers an output signal which will unaergo a predetermined change in response to a predetermined change in the input signal, characterized by error prevention circuitry (US 1 - DSn) incorporated in the TTL circuit fur preventing such response to the said predetermined change in the input signal if a power supply voltage (Vcc) applied to the circuit is at a subnormal value, below a threshold value imposed by the said error prevention circuitry, at which subnormal value the said response could take place in the absence of the said error prevention circuitry.
Claim 9
Dependent Claim
72 words
7 . A TTL circuit as claimed in claim 6, including a transistor (Q 4 ) having its base connected to receive a signal which, in the normal operating condition, will change in response to the said predetermined change in the input signal, wherein the said error prevention circuitry includes at least one semiconductor junction device connected in series with the base-emitter path of the said transistor across the said power supply.
References Cited (Backward Citations)
No citation records indexed.
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