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Patent US4585958A successfully refreshed from Google Patents.
US4585958A
Expired / Lapsed
US
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IC chip with noise suppression circuit
Assignee: Nokia Bell Labs
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Filing: 1983-12-30
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Granted: 1986-04-29
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Expires: 2003-12-30
Abstract
Abstract A microprocessor chip is adapted to maintain its databus at a reference voltage level during idle times between outputs. The arrangement enables like pull-up and pull-down delays as well as low noise levels to be achieved in the output circuits.
Inventors
- 👤 Michael S. Chung
- 👤 Masakazu Shoji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
195 words
In combination (a) a utilization means; (b) a semiconductor integrated circuit chip including a data path for generating binary data signals and an internal databus connected to the data path for receiving the binary signals generated by the data path; (c) an external databus connected for transmitting the binary signals from the internal databus to the utilization means; (d) clock means for producing a clock sequence of alternating driven and idle phases; (e) amplifier means, connected for receiving the binary signals from the internal databus and responsive to the clock sequence of alternating driven and idle phases, for restoring the binary signals to prescribed high and low signal levels in accordance with the binary signals, and connected to the external databus for delivering thereto during each of the driven phases the thus restored binary signals and for floating the external databus during each of the idle phases; and (f) first means for reducing the voltages of the external databus from the high level toward a prescribed intermediate voltage level, which lies between said high and low levels, during each of the idle phases and for floating the external databus during each of the driven phases.
Claim 2
Dependent Claim
195 words
In combination (a) a utilization means; (b) a semiconductor integrated circuit chip including a data path for generating binary data signals and an internal databus connected to the data path for receiving the binary signals generated by the data path; (c) an external databus connected for transmitting the binary signals from the internal databus to the utilization means; (d) clock means for producing a clock sequence of alternating driven and idle phases; (e) amplifier means, connected for receiving the binary signals from the internal databus and responsive to the clock sequence of alternating driven and idle phases, for restoring the binary signals to prescribed high and low signal levels in accordance with the binary signals, and connected to the external databus for delivering thereto during each of the driven phases the thus restored binary signals and for floating the external databus during each of the idle phases; and (f) first means for reducing the voltages of the external databus from the high level toward a prescribed intermediate voltage level, which lies between said high and low levels, during each of the idle phases and for floating the external databus during each of the driven phases.
Claim 3
Dependent Claim
63 words
An IC chip in accordance with claim 1 wherein said first means includes a tristate switch for controlling said external databus, and switching means referenced to the prescribed intermediate voltage level, connected to said external databus, and responsive to a signal fron said tristate switch to reduce the voltage level on said databus toward said intermediate level during each of said idle phases.
Claim 4
Dependent Claim
20 words
An IC chip in accordance with claim 2 wherein said switching means comprises first and second bipolar junction transistors (BJT).
Claim 5
Dependent Claim
37 words
An IC chip in accordance with claim 3 wherein the emitter, base, and collector of said first BJT are connected to said external databus, to the emitter of said second BJT and to a reference potential, respectively.
Claim 6
Dependent Claim
29 words
An IC chip in accordance with claim 4 wherein the base and collector of said second BJT are connected to said tristate switch and to said reference potential respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |