Flip-flop having improved synchronous reset

Claim 2

A flip-flop comprising: data gate circuit means for receiving input data and for generating therefrom first and second complementary internal data signals representative of said input data; master circuit means coupled for receiving a plurality of clock pulses in series and coupled to said data gate circuit means for latching said first and second complementary internal data signals during a predetermined portion of one of said clock pulses; slave circuit means coupled to said master circuit means for storing said latched first and second complementary internal data signals; and reset means coupled to said master circuit means for resetting said latched first and second complementary internal data signals on the occurrence of the next of one of said clock pulses, said reset means including a reset signal having a voltage level greater than said clock pulse, but less than said input data.

Claim 3

The flip-flop according to claim 1 wherein said master circuit means comprises: a pair of differentially connected transistors having their emitters coupled together and connectable to receive said clock pulse; and a first multi-emitter transistor having its collector coupled to the base of a first of said pair of differentially connected transistors, a first emitter coupled to said data gate circuit means and responsive to said first complementary internal data signal, a second emitter coupled to said reset means and responsive to said reset signal.

Claim 4

The flip-flop according to claim 2 wherein said data gate circuit comprises: a first transistor having a base connectable to receive said input data; and a second transistor having a base coupled to a collector of said first transistor, a collector coupled to said first emitter of said first multi-emitter transistor.

Claim 5

The flip-flop according to claim 3 wherein said master circuit means further comprises: a second multi-emitter transistor having a collector coupled to the base of a second of said pair of differentially connected transistors, a first emitter coupled to a collector of said first transistor, a second emitter coupled to the collector of said first of said pair of differentially connected transistors, said first multi-emitter transistor having a third emitter coupled to the collector of said second of said pair of differentially connected transistors.

Claim 6

The flip-flop according to claim 4 wherein said first multi-emitter transistor further comprises a fourth emitter connectable to receive a master reset signal having a voltage level less than the voltage levels of said clock pulse, said reset signal, and said input data.

Claim 7

A flip-flop having a data gate circuit means for receiving input data and for generating therefrom first and second complementary internal data signals representative of said input data, master circuit means for latching said first and second complementary internal data signals and coupled for receiving a clock pulse including a pair of differentially connected transistors having their emitters coupled together and coupled to receive said clock pulse and a first multi-emitter transistor having its collector coupled to the base of one of said pair of differentially connected transistors and a first emitter coupled to said data gate circuit and responsive to said first complementary internal data signal and a second emitter, slave circuit means coupled to said master circuit means for storing said latched first and second complementary internal data signals, the improvement comprising a synchronous reset means coupled to said second emitter for resetting said latched first and second complementary internal data signals on the occurrence of the next clock pulse.

Claim 8

A flip-flop having a data gate circuit means for receiving input data and for generating therefrom first and second complementary internal data signals representative of said input data, master circuit means for latching said first and second complementary internal data signals and coupled for receiving a clock pulse including a pair of differentially connected transistors having their emitters coupled together and coupled to receive said clock pulse and a first multi-emitter transistor having its collector coupled to the base of one of said pair of differentially connected transistors and a first emitter coupled to said data gate circuit and responsive to said first complementary internal data signal and a second emitter, slave circuit means coupled to said master circuit means for storing said latched first and second complementary internal data signals, the improvement comprising a synchronous reset means coupled to said second emitter for resetting said latched first and second complementary internal data signals on the occurrence of the next clock pulse.

Claim 9

The flip-flop according to claim 6 wherein said synchronous reset means includes a reset signal having a voltage level greater than said clock pulse and less than said input data.