US4517475A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Master-slave flip-flop arrangement with slave section having a faster output transistion and a greater resistance to output degradation
Assignee: Motorola Solutions Inc
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Filing: 1983-08-29
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Granted: 1985-05-14
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Expires: 2003-08-29
Abstract
Abstract A TTL flip-flop having improved AC and DC characteristics is provided including a higher resistance to output degradation and quicker transition time from a high state to a low state. The flip-flop includes a master section adapted to receive a data input signal and a clock pulse and includes a first output terminal for providing a Q output signal and a second output terminal for providing a Q output signal. A slave section is coupled between the master section and output buffers for latching the Q and Q outputs. The slave section comprises first and second latch portions, each responsive to a signal from the master section and coupled to one of the output buffers. The latch portions are similar and include a first transistor having a collector coupled to one output terminal and an emitter coupled to the master section. A second transistor has a first emitter coupled to the emitter of the first transistor and a third transistor has a collector coupled to the collector of the first transistor. A fourth transistor has a collector coupled to a second emitter of the second transistor and a base coupled to an emitter of the third transistor.
Inventors
- 👤 Cleon Petty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:52
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289; H03K3/287
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
235 words
A flip-flop having a master section coupled to receive a data input signal and a clock pulse signal, said flip-flop including a first output terminal for providing a Q output signal and a second output terminal for providing a Q output signal, and having a slave section coupled between said first and second output terminals and said master section, said slave section comprising: a first transistor having a collector to said second output terminal and an emitter coupled to said master section; a second transistor having a first emitter coupled to said emitter of said first transistor; a third transistor having a collector coupled to said collector of said first transistor; a fourth transistor having a collector coupled to a second emitter of said second transistor, and a base coupled to an emitter of said third transistor; a fifth transistor having a collector coupling to said frst output terminal and an emitter coupled to said master section; a sixth transistor having a first emitter coupled to said emitter of said fifth transistor and a collector coupled to a base of said third transistor; a seventh transistor having a collector coupled to said collector of said fifth transistor and a base coupled to a collector of said second transistor; and an eighth transistor having a collector coupled to a second emitter of said sixth transistor and a base coupled to an emitter of said seventh transistor.
Claim 2
Dependent Claim
235 words
A flip-flop having a master section coupled to receive a data input signal and a clock pulse signal, said flip-flop including a first output terminal for providing a Q output signal and a second output terminal for providing a Q output signal, and having a slave section coupled between said first and second output terminals and said master section, said slave section comprising: a first transistor having a collector to said second output terminal and an emitter coupled to said master section; a second transistor having a first emitter coupled to said emitter of said first transistor; a third transistor having a collector coupled to said collector of said first transistor; a fourth transistor having a collector coupled to a second emitter of said second transistor, and a base coupled to an emitter of said third transistor; a fifth transistor having a collector coupling to said frst output terminal and an emitter coupled to said master section; a sixth transistor having a first emitter coupled to said emitter of said fifth transistor and a collector coupled to a base of said third transistor; a seventh transistor having a collector coupled to said collector of said fifth transistor and a base coupled to a collector of said second transistor; and an eighth transistor having a collector coupled to a second emitter of said sixth transistor and a base coupled to an emitter of said seventh transistor.
Claim 3
Dependent Claim
24 words
The flip-flop according to claim 1 further comprising a buffer means coupled between said second output terminal and said collector of said first transistor.
Claim 4
Dependent Claim
24 words
The flip-flop according to claim 1 further comprising a buffer means coupled between said first output terminal and said collector of said fifth transistor.
Claim 5
Dependent Claim
287 words
A flip-flop comprising: data gate means coupled for receiving an input data signal and for generating therefrom first and second internal data signals representative of said input data signal; master section means coupled to said data gate means and coupled to receive a clock pulse for latching said internal data signals during a predetermined portion of said clock pulse, said master section means generating a first master signal and a second master signal; and slave means coupled to said master section means for generating therefrom a first output signal and a second output signal, said slave means comprising: a first transistor having a collector coupled for providing said first output signal and an emitter coupled to said master section and responsive to said first master signal; a second transistor having a first emitter coupled to said emitter of said first transistor; a third transistor having a collector coupled to said collector of said first transistor; a fourth transistor having a collector coupled to a second emitter of said second transistor, and a base coupled to an emitter of said third transistor; a fifth transistor having a collector coupled for providing said second output signal and an emitter coupled to said master section and responsive to said second master signal; a sixth transistor having a first emitter coupled to said emitter of said fifth transistor and a collector coupled to a base of said third transistor; a seventh transistor having a collector coupled to said collector of said fifth transistor and a base coupled to a collector of said second transistor; and an eighth transistor having a collector coupled to second emitter of said sixth transistor and a base coupled couupled to an emitter of said seventh transistor.
Claim 6
Dependent Claim
287 words
A flip-flop comprising: data gate means coupled for receiving an input data signal and for generating therefrom first and second internal data signals representative of said input data signal; master section means coupled to said data gate means and coupled to receive a clock pulse for latching said internal data signals during a predetermined portion of said clock pulse, said master section means generating a first master signal and a second master signal; and slave means coupled to said master section means for generating therefrom a first output signal and a second output signal, said slave means comprising: a first transistor having a collector coupled for providing said first output signal and an emitter coupled to said master section and responsive to said first master signal; a second transistor having a first emitter coupled to said emitter of said first transistor; a third transistor having a collector coupled to said collector of said first transistor; a fourth transistor having a collector coupled to a second emitter of said second transistor, and a base coupled to an emitter of said third transistor; a fifth transistor having a collector coupled for providing said second output signal and an emitter coupled to said master section and responsive to said second master signal; a sixth transistor having a first emitter coupled to said emitter of said fifth transistor and a collector coupled to a base of said third transistor; a seventh transistor having a collector coupled to said collector of said fifth transistor and a base coupled to a collector of said second transistor; and an eighth transistor having a collector coupled to second emitter of said sixth transistor and a base coupled couupled to an emitter of said seventh transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-13 | 1988-11-12 | 1989-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-13 | 1992-11-12 | 1993-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-13 | 1996-11-12 | 1997-05-14 | $7700.00 | Window Closed / Lapsed |