Circuit network including integrated circuit flip-flops for digital data processing systems

Claim 2

An integrated circuit flip-flop having a master portion and a slave portion controlled by the master portion, the slave portion including a first and second inverting signal means, each having two inputs and an output coupled to one input of the respective other signal means to provide a set reset type flip-flop as the slave flip-flop, the remaining two inputs defining first and second input terminals of the slave flip-flop, there being means to provide clock pulses, the master portion comprising: a third and a fourth inverting signal means, each having two inputs and an output coupled to one input of the respective other signal means; a fifth inverting signal means having an input and an output; a sixth signal means having two inputs and an output coupled to the input of the fifths signal means, the output of the fifth signal means coupled to one input of the sixth signal means; first gating means combining the output of the fourth signal means and the clock pulses and connected to provide a control signal to the first input terminal of the slave flip-flop; second gating means combining the output of the fifths signal means and the clock pulses and connected to provide a control signal to the second input terminal of the slave flip-flop; first circuit means connected to provide the output of the fifth signal means to the other input of the fourth signal means; second circuit connected to receive a reset input and to provide the reset input to the other input terminal of the third signal means so that the second gating means provides clock variable output in response thereto; and third circuit means connected to receive a set input signal and to provide the set input signal to the other input terminal of the sixth signal means so that the first gating means provides clock variable output.

Claim 3

An integrated circuit flip-flop as in claim 1, there being means to couple the third circuit means to the one input of the fourth signal means.

Claim 4

An integrated circuit flip-flop as in claim 2, there being gating means combining the outputs of the first signal means and of the second circuit means.

Claim 5

An integrated circuit flip-flop as in claim 1, there being fourth circuit means connecting the output of the slave flip-flop to the second circuit means to provide a combined input for the third signal means, there being fifth circuit means connecting the other input of the sixth signal means to the output of the third signal means.

Claim 6

An integrated circuit flip-flop having a master portion and a slave portion controlled by the master portion, the slave portion including a first and second inverting signal means, each having two inputs and an output coupled to one input of the respective other signal means to provide a set reset-type flip-flop as the slave flip-flop, the remaining two inputs defining first and second input terminals of the slave flip-flop, there being means to provide clock pulses, the master portion comprising: first gating means CN1, GR) connected for receiving the clock pulses and haVing an input for receiving a gating signal and having an output connected to the first terminal to provide thereto a clock pulse variable signal varying between a first and a second level when receiving a gating open signal during the reset state, and providing a clock pulse independent signal at the first level to the first terminal when receiving a gating close signal during the set state; second gating means (N3, GS) connected to receive the clock pulses and having an input for receiving a gating signal and having an output connected to the second terminal to provide thereto a clock pulse variable signal, varying between the first and second level when receiving a gating open signal during the set state, and providing a clock pulse independent signal at the first level to the second terminal when receiving a gating closed signal during the reset state; first gate control means (N2) connected to receive a signal corresponding to the output of the first gating means, for input gating, and further connected to receive a set input signal only when the clock pulse dependent output of the first gating means has the first level, and providing an output as gating open signal to the first gating means in response thereto; second gate control means (N4) connected to receive the output of the second gating means and further connected to receive a reset input signal only when the clock pulse dependent output of the first gating means has the first level, and providing an output as gating open signal to the second gating means in response thereto; circuit means interconnecting the first and second gate control means to provide gating signals having opposite gating effects on the first and second gating means, the gate control means changing outputs in response to reception of a set or of a reset signal during a first clock pulse period when the first or the second gating means provide first level outputs in unison, to alter clock pulse dependency of output to be effective upon change over the next second clock pulse period; the circuit means further including means connected to stabilize the gating open and closed signals as established during first clock pulse periods to persist at least during the next second clock pulse period and until reception of a reset or of a set signal, respectively, during a first clock pulse period thereafter, the circuit means including a connection to the output of the slave flip-flop.

Claim 7

An integrated circuit flip-flop having a master portion and a slave portion controlled by the master portion, the slave portion including a first and second inverting signal means, each having two inputs and an output coupled to one input of the respective other signal means to provide a set reset-type flip-flop as the slave flip-flop, the remaining two inputs defining first and second input terminals of the slave flip-flop, there being means to provide clock pulses, the master portion comprising: first gating means CN1, GR) connected for receiving the clock pulses and haVing an input for receiving a gating signal and having an output connected to the first terminal to provide thereto a clock pulse variable signal varying between a first and a second level when receiving a gating open signal during the reset state, and providing a clock pulse independent signal at the first level to the first terminal when receiving a gating close signal during the set state; second gating means (N3, GS) connected to receive the clock pulses and having an input for receiving a gating signal and having an output connected to the second terminal to provide thereto a clock pulse variable signal, varying between the first and second level when receiving a gating open signal during the set state, and providing a clock pulse independent signal at the first level to the second terminal when receiving a gating closed signal during the reset state; first gate control means (N2) connected to receive a signal corresponding to the output of the first gating means, for input gating, and further connected to receive a set input signal only when the clock pulse dependent output of the first gating means has the first level, and providing an output as gating open signal to the first gating means in response thereto; second gate control means (N4) connected to receive the output of the second gating means and further connected to receive a reset input signal only when the clock pulse dependent output of the first gating means has the first level, and providing an output as gating open signal to the second gating means in response thereto; circuit means interconnecting the first and second gate control means to provide gating signals having opposite gating effects on the first and second gating means, the gate control means changing outputs in response to reception of a set or of a reset signal during a first clock pulse period when the first or the second gating means provide first level outputs in unison, to alter clock pulse dependency of output to be effective upon change over the next second clock pulse period; the circuit means further including means connected to stabilize the gating open and closed signals as established during first clock pulse periods to persist at least during the next second clock pulse period and until reception of a reset or of a set signal, respectively, during a first clock pulse period thereafter, the circuit means including a connection to the output of the slave flip-flop.

Claim 8

Flip-flop as in claim 5, the circuit means including a gate combining the output of the second gate control means and of the set signal input to provide a control signal, effective as gating signal for the second gating means as well as set input for the first gate control means, to obtain set override reset operation.

Claim 9

In a data processing system, a first flip-flop constructed as integrated circuit and having set and reset input terminals and output terminals; a plurality of second flip-flops each being also constructed as integrated circuit and each having input and output terminals; a circuit logic including discrete diode-type elements, resistor elements and connection means for interconnecting output terminals of said second flip-flops to form composite input signals and for applying same to said input terminals of said first flip-flop; first voltage-supply means connected to operate said first and second flip-flops at a relatively low voltage; second voltage-supply means connected to operate the elements of the circuit logic at a substantially higher voltage; circuit means connecting the circuit logic to said terminals and further connected to the first and to the second voltage-supply means to adapt the level of the composite signals as formed in the circuit logic to a lower level for the first flip-flop; and at least one diode for each input terminal, respectively connected in series between the circuit means and each said input terminal of the first flip-flop, at a polarity in forward direction as to the signal poLarity.

Claim 10

In a data processing system, a first flip-flop constructed as integrated circuit and having set and reset input terminals and output terminals; a plurality of second flip-flops each being also constructed as integrated circuit and each having input and output terminals; a circuit logic including discrete diode-type elements, resistor elements and connection means for interconnecting output terminals of said second flip-flops to form composite input signals and for applying same to said input terminals of said first flip-flop; first voltage-supply means connected to operate said first and second flip-flops at a relatively low voltage; second voltage-supply means connected to operate the elements of the circuit logic at a substantially higher voltage; circuit means connecting the circuit logic to said terminals and further connected to the first and to the second voltage-supply means to adapt the level of the composite signals as formed in the circuit logic to a lower level for the first flip-flop; and at least one diode for each input terminal, respectively connected in series between the circuit means and each said input terminal of the first flip-flop, at a polarity in forward direction as to the signal poLarity.

Claim 11

In a system as in claim 7, the circuit means including a second diode connected series with one of said diodes but for oppositely directed current conduction, the second diode connected to the first and second voltage-supply means to be biased in forward direction by the differential of the two voltages.