US4575923A
Expired / Lapsed
US
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Method of manufacturing a high resistance layer having a low temperature coefficient of resistance and semiconductor device having such high resistance layer
Assignee: Philips North America LLC
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Filing: 1983-04-06
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Granted: 1986-03-18
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Expires: 2003-04-06
Abstract
Abstract The present invention provides a high resistance film with a low temperature coefficient of resistance. Such films can be used as resistors in integrated and hybrid circuits, as well as resistive layers in passivating circuits for high-voltage devices. In the latter circuits, the passivating layers shield the device from the detrimental influence of external or internal electric fields. The ability to obtain a low temperature coefficient of resistance enables obtaining a high sheet resistance without being influenced by changing temperatures.
Inventors
- 👤 Emil Arnold
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:36
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; Y; Y10; Y10T; Y10T428/00; Y10T428/12; Y10T428/12493; Y10T428/12674
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
83 words
Method of manufacturing a solid state device having a high resistivity film with a low temperature coefficient of resistance comprising the steps of forming a thin semi-insulating film, said film consisting of small silicon crystallites embedded in a silicon dioxide matrix, carrying out ion implantation of said film by one of arsenic or phosphorus ions to produce a resistive layer having a low temperature coefficient of resistance, forming electrode regions with respect to said film, and annealing said film at approximately 900° C.
Claim 2
Dependent Claim
83 words
Method of manufacturing a solid state device having a high resistivity film with a low temperature coefficient of resistance comprising the steps of forming a thin semi-insulating film, said film consisting of small silicon crystallites embedded in a silicon dioxide matrix, carrying out ion implantation of said film by one of arsenic or phosphorus ions to produce a resistive layer having a low temperature coefficient of resistance, forming electrode regions with respect to said film, and annealing said film at approximately 900° C.
Claim 3
Dependent Claim
19 words
A method according to claim 1, wherein said resistive layer is produced throughout the thickness of said thin film.
Claim 4
Dependent Claim
24 words
A method according to claim 1, wherein said resistive layer is produced as a single layer formed into one surface of said thin film.
Claim 5
Dependent Claim
29 words
A method according to claim 2, wherein said ion implantation is carried out by a three-stage ion implantation technique to achieve uniform resistance throughout the thickness of said film.
Claim 6
Dependent Claim
19 words
A method according to claim 2, wherein said electrode regions are formed on opposite sides of said thin film.
Claim 7
Dependent Claim
54 words
A method according to claim 2, wherein said thin film is formed on a silicon substrate, one of said electrode regions is formed of a doped region between said thin film and said silicon substrate, and another electrode region is formed as a metal layer on said thin film opposite to said doped region.
Claim 8
Dependent Claim
28 words
A method according to claim 3, wherein said thin film is formed on a substate with said resistive layer being at said one surface opposite to said substrate.
Claim 9
Dependent Claim
27 words
A method according to claim 3, wherein a single ion implantation is carried out with arsenic ions at 10 14 ions per cm 2 at 25 KeV.
Claim 10
Dependent Claim
15 words
A method according to claim 4, wherein said film has a thickness of about 1000A.
Claim 11
Dependent Claim
55 words
A method according to claim 4, wherein said ion implantation is of arsenic ions, and wherein said three-step ion implantation technique includes implantation of arsenic ions at 2×10 14 ions per cm 2 at 145 KeV, 1×10 14 ions per cm 2 at 70 KeV, and 6×10 13 ions per cm 2 at 25 KeV.
Claim 12
Dependent Claim
20 words
A method according to claim 7, wherein said electrode regions are formed at said one surface opposite to said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-17 | 1989-09-16 | 1990-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-17 | 1993-09-16 | 1994-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-17 | 1997-09-16 | 1998-03-18 | $7700.00 | Window Closed / Lapsed |