US4564772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latching circuit speed-up technique
Assignee: International Business Machines Corp
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Filing: 1983-06-30
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Granted: 1986-01-14
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Expires: 2003-06-30
Abstract
Abstract A latching circuit with reduced signal delay is disclosed comprising a latch and an output logic function circuit. The same signals are applied to the output gate of the latch and to the logic function circuit, whereby the output gate and the logic function circuit effectively are connected in parallel, rather than in series, to eliminate one level of logic delay. An additional logic signal is applied only to the logic function circuit but not to the latch. Provision can be made for applying inverted data to the latch in the event that the latch and the logic function circuit are implemented with NAND or NOR gates.
Inventors
- 👤 Gerald A. Maley
- 👤 Douglas W. Westcott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:58
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
122 words
In a latching circuit array of logic gates wherein a latch comprising some of said gates and responsive to a logic signal is drivably connected to an output logic circuit comprising at least one other of said gates, said latch having an output gate having at least two inputs, said output gate and said one other of said gates being of the same kind, means for connecting each of the inputs of said output gate of said latch to respective ones of inputs of said one other of said gates, and means for applying at least one additional signal to at least one additional input of said one other of said gates but not to any of said gates of said latch.
Claim 2
Dependent Claim
122 words
In a latching circuit array of logic gates wherein a latch comprising some of said gates and responsive to a logic signal is drivably connected to an output logic circuit comprising at least one other of said gates, said latch having an output gate having at least two inputs, said output gate and said one other of said gates being of the same kind, means for connecting each of the inputs of said output gate of said latch to respective ones of inputs of said one other of said gates, and means for applying at least one additional signal to at least one additional input of said one other of said gates but not to any of said gates of said latch.
Claim 3
Dependent Claim
19 words
The circuit of claim 1 wherein said output gate and said one other of said gates are NAND gates.
Claim 4
Dependent Claim
19 words
The circuit of claim 1 wherein said output gate and said one other of said gates are NOR gates.
Claim 5
Dependent Claim
16 words
The circuit of claim 1 wherein all of said logic gates are of the same kind.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-13 | 1989-07-15 | 1990-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-13 | 1993-07-15 | 1994-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-13 | 1997-07-15 | 1998-01-14 | $7700.00 | Window Closed / Lapsed |