← Back to Patent Explorer
US4439690A Expired / Lapsed US ⏱️ 0.0 years remaining

Three-gate hazard-free polarity hold latch

Assignee: International Business Machines Corp
•
Filing: 1982-04-26
•
Granted: 1984-03-27
•
Expires: 2002-04-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A hazard-free latch is disclosed comprising three NAND logic gates, one of the gates, in combination with its output loading, being relatively fast and another of the gates, in combination with its output loading, being relatively slow. Both gates receive an input clock signal. Input data is applied to the third gate. The output of the fast gate is connected to another input of the slow gate. The outputs of the third and the slow gates are connected to an output terminal and to another input of the fast gate.

Inventors

  • 👤 Gerald A. Maley
  • 👤 Raymond H. Warren
  • 👤 Douglas W. Westcott

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 22:15
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 127 words
A latch comprising three logic gates, each having a plurality of inputs and one output, one of said gates in combination with its output loading being relatively faster in operation than a second of said gates in combination with its output loading, one input of said one and said second gates being connected to receive a clock input, the output of said one gate being connected to one input of a third of said gates and to another input of said second gate, another input of said third gate being connected to receive a data input, the output of said third and said second gates being connected to an output terminal, and the output of said second gate being connected to another input of said first gate.
Claim 2
Dependent Claim 127 words
A latch comprising three logic gates, each having a plurality of inputs and one output, one of said gates in combination with its output loading being relatively faster in operation than a second of said gates in combination with its output loading, one input of said one and said second gates being connected to receive a clock input, the output of said one gate being connected to one input of a third of said gates and to another input of said second gate, another input of said third gate being connected to receive a data input, the output of said third and said second gates being connected to an output terminal, and the output of said second gate being connected to another input of said first gate.
Claim 3
Dependent Claim 33 words
The latch defined in claim 1 wherein said three gates are NAND gates and said outputs of said third and said second gates are connected via a dot AND to said output terminal.
Claim 4
Dependent Claim 33 words
The latch defined in claim 1 wherein said three gates are NOR gates and said outputs of said third and said second gates are connected via a dot OR to said output terminal.
Claim 5
Dependent Claim 96 words
The latch defined in claim 1 and further including a fourth logic gate having a plurality of inputs and one output, the output of said fourth gate being connected to said output terminal, one input of said fourth gate being connected to receive a second data input, a second input of said fourth gate being connected to the output of said one gate, a third input of said fourth gate being connected to receive said clock input, and a third input of said first, second and third gates being connected to receive a second clock signal.
Claim 6
Dependent Claim 35 words
The latch defined in claim 4 wherein said four gates are NAND gates and said outputs of said fourth, said third and said second gates are connected via a dot AND to said output terminal.
Claim 7
Dependent Claim 35 words
The latch defined in claim 4 wherein said four gates are NOR gates and said outputs of said fourth, said third and said second gates are connected via a dot OR to said output terminal.

References Cited (Backward Citations)

US3603815A Cited
US3740590A Cited
US4160173A Cited
US4283640A Cited
US4374331A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-03-27 1987-09-26 1988-03-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-03-27 1991-09-26 1992-03-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-03-27 1995-09-26 1996-03-27 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag