US4283640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
All-NPN transistor driver and logic circuit
Assignee: International Business Machines Corp
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Filing: 1979-10-05
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Granted: 1981-08-11
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Expires: 1999-10-05
Abstract
Abstract An all-NPN bipolar transistor driver circuit characterized by low standby power dissipation and fast response, particularly at high input driving conditions. The bases of a pair of NPN transistors are commonly connected to an input terminal. The emitter of a third NPN transistor is connected to the collector of one transistor of the transistor pair and to an output terminal. The collector of the other transistor of the transistor pair is connected to the base of the third NPN transistor. The base and collector of the third NPN transistor are coupled to a first biasing means. The emitters of the transistor pair are connected to a second biasing means through respective resistors so that those emitters may be independently biased. The values of the biasing means are set, relative to the lowest input voltage excursion occurring at the input terminal so that no current flows through transistor pair during the lowest input voltage excursion. Various circuit extensions, based on the above driver circuit, are also described to provide logic functions represented by output logic signals which are in-phase as well as out-of-phase relative to the applied input logic signals.
Inventors
- 👤 Richard R. Konian
- 👤 James L. Walsh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:24
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6242; H03K17/625; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
165 words
An NPN transistor driver circuit comprising: a first pair of NPN transistors, the base of said pair of transistors being connected to an input terminal, a third NPN transistor, the emitter of said third transistor being connected to the collector of one transistor of said transistor pair and to an output terminal, the collector of the other transistor of said transistor pair being connected to the base of said third transistor, the base and collector of said third transistor being connected to first biasing means, a pair of resistors, the emitters of the transistors of said transistor pair being connected through respective ones of said pair of resistors to second biasing means, a source of first input signal coupled to said input terminal, the voltages of said first and second biasing means being set relative to the lowest voltage excursion of said input signal, so that substantially no current flows through at least said one transistor of said transistor pair during said lowest voltage excursion.
Claim 2
Dependent Claim
165 words
An NPN transistor driver circuit comprising: a first pair of NPN transistors, the base of said pair of transistors being connected to an input terminal, a third NPN transistor, the emitter of said third transistor being connected to the collector of one transistor of said transistor pair and to an output terminal, the collector of the other transistor of said transistor pair being connected to the base of said third transistor, the base and collector of said third transistor being connected to first biasing means, a pair of resistors, the emitters of the transistors of said transistor pair being connected through respective ones of said pair of resistors to second biasing means, a source of first input signal coupled to said input terminal, the voltages of said first and second biasing means being set relative to the lowest voltage excursion of said input signal, so that substantially no current flows through at least said one transistor of said transistor pair during said lowest voltage excursion.
Claim 3
Dependent Claim
17 words
The circuit defined in claim 1 wherein each of said resistors is shunted by a respective capacitor.
Claim 4
Dependent Claim
16 words
The circuit defined in claim 1 wherein said output terminal is connected to a capacitive load.
Claim 5
Dependent Claim
48 words
The circuit defined in claim 1 wherein the voltages of said first and second biasing means are set, relative to the lowest voltage excursion of said input signal, so that substantially no current flows through either of said transistors of said transistor pair during said lowest voltage excursion.
Claim 6
Dependent Claim
62 words
The circuit defined in claim 4 and further including additional pairs of NPN transistors, each said additional pair of transistors being connected in parallel with said first pair of transistors, each said additional pair of transistors having commonly connected bases, and additional sources of input signals, each said additional source being connected to a respective one of said additional pairs of transistors.
Claim 7
Dependent Claim
39 words
The circuit defined in claim 1 and further including circuit means coupled to the emitter of said other transistor of said transistor pair for providing an output signal which is in phase with respect to said first input signal.
Claim 8
Dependent Claim
23 words
The circuit defined in claim 6 wherein said circuit means, together with said other transistor of said transistor pair, comprises a current switch.
Claim 9
Dependent Claim
27 words
The circuit defined in claim 7 wherein said pair of resistors connect said emitters of said transistors of said first pair of transistors to respective biasing means.
Claim 10
Dependent Claim
27 words
The circuit defined in claim 8 wherein only said resistor connected to the emitter of said one transistor of said transistor pair is shunted by a capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-10 | 1985-02-09 | 1985-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-10 | 1989-02-09 | 1989-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-10 | 1993-02-09 | 1993-08-11 | $7700.00 | Window Closed / Lapsed |