High speed, low dissipation logic gates

Claim 1

A LOGIC CIRCUIT COMPRISING: AN INPUT CIRCUIT FOR RECEIVING BIVALUED INPUT SIGNALS FOR DEVELOPING BIVALUED SIGNALS AT A CIRCUIT POINT; A FIRST AND SECOND TRANSISTOR EACH HAVING A BASE, COLLECTOR AND EMITTER ELECTRODE AND HAVING THEIR BASE ELECTRODES COMMONLY CONNECTED TOGETHER AND THEIR EMITTER ELECTRODES CONNECTED TO A POINT OF REFERENCE POTENTIAL; MEANS CONNECTING SAID CIRCUIT POINT WITH SAID COMMONLY CONNECTED BASE ELECTRODES; AN OUTPUT JUNCTION CONNECTED TO THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR; A THIRD TRANSISTOR HAVING A BASE, COLLECTOR AND EMITTER ELECTRODE AND HAVING ITS BASE ELECTRODE CONNECTED TO THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR AND EMITTER ELECTRODE CONNECTED TO SAID OUTPUT JUNCTION; A FIRST RESISTOR CONNECTED TO SAID COMMON POINT FOR SUPPLYING BASE CURRENT TO SAID FIRST AND SECOND TRANSISTORS; A SECOND RESISTOR CONNECTED TO THE COLLECTOR OF SAID FIRST, AND BASE ELECTRODE OF SAID THIRD TRANSISTOR; A THIRD RESISTOR CONNECTED TO THE COLLECTOR ELECTRODE OF SAID THIRD TRANSISTOR; OUTPUT LEAD MEANS CONNECTED TO SAID OUTPUT JUNCTION; AND MEANS FOR CONNECTING SAID RESISTORS TO A SOURCE OF OPERATING POTENTIAL.