Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
227 words
In a multiplex system, a transmission gating circuit for controlling access of a serial binary input signal to a selected subscriber terminal, the input signal having an address portion and an information portion, each portion comprising a plurality of data bits, said transmission gating circuit comprising: a first input port for connection to a source of input signal and an output port for connection to the subscriber terminal, second and third input ports for connection to respective sources of first and second control signals, a comparator circuit comprising an exclusive-OR gate having a first input terminal connected to the first input port, a second input terminal connected to a pattern generator adapted to generate a signal which corresponds to a predetermined address, and an output terminal for obtaining a first output signal, a first AND gating means connected in series between the output terminal of the first exclusive-OR gate and the output port, a gating circuit including a single memory unit, said gating circuit being responsive to said first output signal and to said first and second control signals for inhibiting said first AND gating means during the address portion of the input signal and for allowing said first AND gating means to pass the information portion of the input signal when the address portion of the input signal matches the address generated by the pattern generator.
Claim 2
Dependent Claim
227 words
In a multiplex system, a transmission gating circuit for controlling access of a serial binary input signal to a selected subscriber terminal, the input signal having an address portion and an information portion, each portion comprising a plurality of data bits, said transmission gating circuit comprising: a first input port for connection to a source of input signal and an output port for connection to the subscriber terminal, second and third input ports for connection to respective sources of first and second control signals, a comparator circuit comprising an exclusive-OR gate having a first input terminal connected to the first input port, a second input terminal connected to a pattern generator adapted to generate a signal which corresponds to a predetermined address, and an output terminal for obtaining a first output signal, a first AND gating means connected in series between the output terminal of the first exclusive-OR gate and the output port, a gating circuit including a single memory unit, said gating circuit being responsive to said first output signal and to said first and second control signals for inhibiting said first AND gating means during the address portion of the input signal and for allowing said first AND gating means to pass the information portion of the input signal when the address portion of the input signal matches the address generated by the pattern generator.
Claim 3
Dependent Claim
109 words
A transmission gating circuit as defined in claim 1 wherein said memory unit is a triggerable flip-flop and wherein the remainder of the gating circuit comprises: a second AND gating means responsive to said first output signal and to said first control signal and to the complement of the output signal from the flip-flop for producing a second output signal, a third AND gating means responsive to the output signal from the flip-flop, to said second control signal and to the complement of said first output signal for producing a third output signal, an OR gating means responsive to said second and third output signals for triggering said flip-flop.
Claim 4
Dependent Claim
68 words
A transmission gating circuit as defined in claim 2 wherein said first AND gating means is an AND gate having an output terminal connEcted to the subscriber terminal, a first input terminal connected to the output terminal of the exclusive-OR gate, a second input terminal connected to the third input port through an inverter gate and a third input terminal connected to the output terminal of the flip-flop.
Claim 5
Dependent Claim
30 words
A transmission gate circuit as defined in claim 3 wherein said second and third AND gating means are AND gates and wherein said OR gating means is an OR gate.