Di-phase pulse receiving system

Claim 2

In a di-phase pulse receiving system of the type which receives a plurality of transmitted serial di-phase data bits and of the type which includes a positive peak detector for providing a first pulse upon detecting a positive di-phase signal portion and a negative peak detector for providing a second pulse upon detecting a negative di-phase signal portion, a control means for converting the serial di-phase data bits into parallel data bits having corresponding discrete logic levels, said control means comprising: first set means coupled to the positive peak detector and responsive to the first pulses for being set upon the detection of a positive di-phase signal portion, second set means coupled to the negative peak detector and responsive to the second pulses for being set upon the detection of a negative di-phase signal portion, and shift register means having a first input coupled to said first set means, a second input coupled to said second set means, a clock input coupled to the positive peak detector for being clocked by the trailing edge of the first pulses, and a plurality of parallel outputs, said shift register means being responsive to the coincidence of said first and second set means being set upon being clocked to thereby shift a first logic level to said parallel outputs and responsive to only said first set means being set upon being clocked to thereby shift a second logic level to said parallel outputs.

Claim 3

A control means in accordance with claim 1 further including reset means for resetting said first and second set means and wherein said first set means includes a first reset input and said second set means includes a second reset input, said reset means comprising a first input coupled to the positive peak detector, a second input coupled to the negative peak detector, a third input coupled to said first set means, a fourth input coupled to said second means, and an output coupled to said reset inputs whereby, said reset means resets the control means after receipt of each di-phase data bit by resetting said first and second set means responsive to said first and second set means being set and the first and second pulses.

Claim 4

A control means in accordance with claim 2 wherein said reset means comprises a NAND gate.

Claim 5

A control means in accordance with claim 1 wherein first and second set means comprise RS flip-flops.

Claim 6

A control means in accordance with claim 1 wherein said shift register means comprises at least one shift register and wherein said shift register includes an AND gate comprising said first and second inputs for detecting the coincident set condition of said first and second set means.

Claim 7

In a di-phase pulse receiving system of the type which receives a plurality of transmitted serial di-phase data bits and of the type which includes a positive peak detector for providing a first pulse upon detecting a positive di-phase signal portion and a negative peak detector for providing a second pulse upon detecting a negative di-phase signal portion, a control means for converting the serial di-phase data bits into parallel data bits having corresponding discrete logic levels, said control means comprising: a first RS flip-flop having a first set input, a first reset input and an output, said first set input being coupled to the positive peak detector and responsive to the first pulses whereby upon the detection of a positive di-phase signal portion the positive peak detector sets said first RS flip-flop; a second RS flip-flop having a second set input, a second reset input, and an output, said second set input being coupled to the negative peak detector and responsive to the second pulses whereby upon the detection of a negative di-phase signal portion the negative peak detector sets said second RS flip-flop; and a shift register including an AND gate having a first input coupled to said first RS flip-flop output and a second input coupled to said second RS flip-flop output, a clock input coupled to the positive peak detector for being clocked by the trailing edge of the first pulses, and a plurality of parallel outputs, said AND gate being responsive to the coincident of said first and second RS flip-flops being in the set condition when said shift register is clocked at said clock input to cause said shift register to shift a first logic level to said parallel outputs and said AND gate being responsive to only said first RS flip-flop being in the set condition when said shift register is clocked at said clock input to cause said shift register to shift a second logic level to said parallel outputs.

Claim 8

In a di-phase pulse receiving system of the type which receives a plurality of transmitted serial di-phase data bits and of the type which includes a positive peak detector for providing a first pulse upon detecting a positive di-phase signal portion and a negative peak detector for providing a second pulse upon detecting a negative di-phase signal portion, a control means for converting the serial di-phase data bits into parallel data bits having corresponding discrete logic levels, said control means comprising: a first RS flip-flop having a first set input, a first reset input and an output, said first set input being coupled to the positive peak detector and responsive to the first pulses whereby upon the detection of a positive di-phase signal portion the positive peak detector sets said first RS flip-flop; a second RS flip-flop having a second set input, a second reset input, and an output, said second set input being coupled to the negative peak detector and responsive to the second pulses whereby upon the detection of a negative di-phase signal portion the negative peak detector sets said second RS flip-flop; and a shift register including an AND gate having a first input coupled to said first RS flip-flop output and a second input coupled to said second RS flip-flop output, a clock input coupled to the positive peak detector for being clocked by the trailing edge of the first pulses, and a plurality of parallel outputs, said AND gate being responsive to the coincident of said first and second RS flip-flops being in the set condition when said shift register is clocked at said clock input to cause said shift register to shift a first logic level to said parallel outputs and said AND gate being responsive to only said first RS flip-flop being in the set condition when said shift register is clocked at said clock input to cause said shift register to shift a second logic level to said parallel outputs.

Claim 9

A control means in accordance with claim 6 further including a reset means comprising a NAND gate, said NAND gate including a first input coupled to the positive peak detector, a second input coupled to the negative peak detector, a third input coupled to said first RS flip-flop output, a fourth input coupled to said second RS flip-flop output, and an output coupled to said first and second reset inputs whereby, said NAND gate resets the control means after receipt of each di-phase data bit by resetting said first and second RS flip-flops responsive to said first and second RS flip-flops being in the set condition and the first and second pulses.