US3610982A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Quaternary phase difference sign determining device
Assignee: Licentia Patent Verwaltungs GmbH
•
Filing: 1970-04-29
•
Granted: 1971-10-05
•
Expires: 1990-04-29
Abstract
Abstract A device which interprets the sign components of pairs of consecutive pulses which have been demodulated from pulse data transmitted with quaternary phase difference keying, the device employing a pair of flip-flops with preliminary memory whose outputs are connected to a second pair of similar flip-flops. For each pair of consecutive pulses, NOR gates are used to determine the coincidence or lack of coincidence of the sign components of the pair of pulses and further NOR gates are used to determine the coincidence or lack of coincidence of the sign components of the first of the pulse pair. The second set of NOR gates controls a device which determines the sequence of transmission of the bits determined by the first set of NOR gates, thus clearly identifying and transmitting the binary word according to the phase difference.
Inventors
- 👤 Bernhard Rall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:06
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
186 words
A circuit for determining the phase difference between a pair of consecutive pulses, each having two sign components relating to a quaternary phase plane, comprising, in combination: a first pair of bistable flip-flops to which the sign components of consecutive pulses are applied, a second pair of bistable flip-flops having their inputs connected to the outputs of the first pair of bistable flipflops, means for applying a sequence of clock pulses simultaneously to all of said bistable flip-flops, a first pair of gates, connected to produce outputs respectively in response to coincidence and noncoincidence of sign components of each consecutive pair of pulses applied to said first pair of bistable flip-flops, a second pair of gates connected for determining the coincidence and noncoincidence respectively of the outputs of said second pair of bistable flip-flops, a pair of output gates connected to receive as respective inputs thereto the outputs of said first pair of gates; and means having outputs connected as further inputs to said output gates for determining the sequence of transmission from said output gates, said means being controlled by said second pair of gates.
Claim 2
Dependent Claim
186 words
A circuit for determining the phase difference between a pair of consecutive pulses, each having two sign components relating to a quaternary phase plane, comprising, in combination: a first pair of bistable flip-flops to which the sign components of consecutive pulses are applied, a second pair of bistable flip-flops having their inputs connected to the outputs of the first pair of bistable flipflops, means for applying a sequence of clock pulses simultaneously to all of said bistable flip-flops, a first pair of gates, connected to produce outputs respectively in response to coincidence and noncoincidence of sign components of each consecutive pair of pulses applied to said first pair of bistable flip-flops, a second pair of gates connected for determining the coincidence and noncoincidence respectively of the outputs of said second pair of bistable flip-flops, a pair of output gates connected to receive as respective inputs thereto the outputs of said first pair of gates; and means having outputs connected as further inputs to said output gates for determining the sequence of transmission from said output gates, said means being controlled by said second pair of gates.
Claim 3
Dependent Claim
33 words
The circuit according to claim 1, wherein said means comprises a further bistable flip-flop connected as a binary counter and having the outputs of said second pair of gates connected as inputs thereto.
Claim 4
Dependent Claim
31 words
The circuit according to claim 2 further comprising means connected for delivering a first train of clock pulses to said second pair of gates for controlling the delivery of signals therefrom.
Claim 5
Dependent Claim
36 words
The circuit according to claim 3, further comprising means for controlling said further flip-flop according to a second train of clock pulses displaced by a half period with respect to said first train of clock pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-04 | 1975-04-05 | 1975-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-04 | 1979-04-05 | 1979-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-04 | 1983-04-05 | 1983-10-05 | $7700.00 | Window Closed / Lapsed |