US3882325A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-chip latching circuit for avoiding input-output pin limitations
Assignee: International Business Machines Corp
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Filing: 1973-12-10
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Granted: 1975-05-06
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Expires: 1993-12-10
Abstract
Abstract A multi-chip latching circuit comprising first and second chips each including a respective latching circuit and a third chip including a logic circuit which functions as an OR circuit for rising input signals and as an AND circuit for falling input signals. The output signals from the first two chips provide the input signals to the third chip. The three chips, in combination, act as a single composite latching circuit responsive to a plurality of set signal inputs and a plurality of reset signal inputs. The total number of set and reset signal inputs, are divided between the first and second chips with one chip receiving at least one set signal and its associated reset signal and the other chip receiving the remainder of the total number of set and reset signal inputs. There is no direct signal connection between the first and second chips.
Inventors
- 👤 Fred Elias Sakalay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:30
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
119 words
A composite latching circuit receiving a plurality of set signals and a plurality of reset signals comprising: a first constituent latching circuit receiving at least one of said set signals and the associated one of said reset signals, a second constituent latching circuit receiving the remainder of said plurality of set and reset signals, each said constituent latching circuit providing an output signal representing the state thereof, and a logic circuit operative as a positive OR circuit for input signal amplitude changes in one direction and as a positive AND circuit for input signal amplitude changes in the opposite direction, said output signal from each said constituent latching circuit being applied to said logic circuit as said input signals.
Claim 2
Dependent Claim
119 words
A composite latching circuit receiving a plurality of set signals and a plurality of reset signals comprising: a first constituent latching circuit receiving at least one of said set signals and the associated one of said reset signals, a second constituent latching circuit receiving the remainder of said plurality of set and reset signals, each said constituent latching circuit providing an output signal representing the state thereof, and a logic circuit operative as a positive OR circuit for input signal amplitude changes in one direction and as a positive AND circuit for input signal amplitude changes in the opposite direction, said output signal from each said constituent latching circuit being applied to said logic circuit as said input signals.
Claim 3
Dependent Claim
24 words
The composite latching circuit defined in claim 1 wherein said one direction is a rising direction and said opposite direction is a falling direction.
Claim 4
Dependent Claim
145 words
The composite latching circuit defined in claim 1 wherein said logic circuit comprises: a third latching circuit receiving said output signals from said first and second constituent latching circuits, said third latching circuit being set when both said output signals are of a first amplitude and being reset when both said output signals are of a second amplitude, first, second and third AND gates, an OR gate, and an inverter, the output of said third latching circuit being coupled to said first and third AND gates by said inverter, said output signal from one of said constituent latching circuits being applied to said first and second AND gates, said output signal from the other of said constituent latching circuits being applied to said second and third AND gates, and the output of said first, second and third AND gates being coupled to said OR gate.
Claim 5
Dependent Claim
19 words
The composite latching circuit defined in claim 3 wherein said first amplitude is high relative to said second amplitude.
Claim 6
Dependent Claim
102 words
The composite latching circuit defined in claim 3 wherein said third latching circuit comprises: fourth, fifth and sixth AND gates and a second OR gate, said output signal from one of said constituent latching circuits being applied to said fourth and fifth AND gates, said output signal from the other of said constituent latching circuits being applied to said fifth and sixth AND gates, the output of said fourth, fifth and sixth AND gates being coupled to said second OR gate, and the output of said Second OR gate being coupled to said fourth and sixth AND gates and to said inverter.
Claim 7
Dependent Claim
20 words
The composite latching circuit defined in claim 5 wherein said second and fifth AND gates are combined as one structure.
Claim 8
Dependent Claim
147 words
A logic circuit operative as an OR circuit for input signal amplitude changes in one direction and as an AND circuit for input signal amplitude changes in the opposite direction, said logic circuit comprising: a latching circuit receiving first and second input signals, said latching circuit being set when both said input signals are of a first amplitude and being reset when both set input signals are of a second amplitude, first, second and third AND gates, an OR gate, and an inverter, the output of said latching circuit being coupled to said first and third AND gates by said inverter, one of said input signals being applied to said first and second AND gates, the other of said input signals being applied to said second and third AND gates, and the output of said first, second and third AND gates being coupled to said OR gate.
Claim 9
Dependent Claim
147 words
A logic circuit operative as an OR circuit for input signal amplitude changes in one direction and as an AND circuit for input signal amplitude changes in the opposite direction, said logic circuit comprising: a latching circuit receiving first and second input signals, said latching circuit being set when both said input signals are of a first amplitude and being reset when both set input signals are of a second amplitude, first, second and third AND gates, an OR gate, and an inverter, the output of said latching circuit being coupled to said first and third AND gates by said inverter, one of said input signals being applied to said first and second AND gates, the other of said input signals being applied to said second and third AND gates, and the output of said first, second and third AND gates being coupled to said OR gate.
Claim 10
Dependent Claim
87 words
The logic circuit defined in claim 7 wherein said latching circuit comprises: fourth, fifth and sixth AND gates and a second OR gate, said one input signal being applied to said fourth and fifth AND gates, said other input signal being applied to said fifth and sixth AND gates, the output of said fourth, fifth and sixth AND gates being coupled to said second OR gate, and the output of said second OR gate being coupled to said fourth and sixth AND gates and to said inverter.
Claim 11
Dependent Claim
19 words
The latching circuit defined in claim 8 wherein said second and fifth AND gates are combined as one structure.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |