Patent US3091209A successfully refreshed from Google Patents.
Patent US4554729A successfully refreshed from Google Patents.
US4554729A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1982-01-22
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Granted: 1985-11-26
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Expires: 2002-01-22
Abstract
Abstract Herein disclosed is a semiconductor memory device which is composed of a peripheral circuit unit equipped with a gate protection circuit having a protection resistor and a memory cell unit so that it can be used as an MISFET type static RAM and which is characterized in that the protection resistor is made of a polycrystalline silicon film having substantially the same resistivity as that of an overlying polycrystalline silicon film formed to merge into the load resistor of the memory cell unit.
Inventors
- 👤 Nobuyoshi Tanimura
- 👤 Tokumasa Yasui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:55
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10D88/00; H10D89/00; H10D89/60; H10D89/601; H10D89/911; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
225 words
A process for fabricating a semiconductor memory device having MIS transistors composing memory cells, the memory cells having load resistors, the load resistors being connected to a power supply line, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuit being connected with a protection resistor, comprising the steps of: forming a first film of an electrically conductive material, which serves as the gate of the MIS transistors composing memory cells of the semiconductor memory device, over a semiconductor substrate, said first film having a first resistivity; forming an insulation film to cover the semiconductor substrate which is formed with each of the MIS transistors composing said memory cells; and forming second films, which second films include a layer of polycrystalline silicon, which second films respectively serve as each load resistor of each of said memory cells, as a wiring for connecting the load resistors with a power supply line and as the protection resistor connected with the gate of at least one of the MIS transistors composing peripheral circuits, over said insulation film covering said semiconductor substrate, the resistivity of the second films serving as said protection resistor and as said wiring being lower than that of the second film serving as said load resistor and higher than that of said first film.
Claim 2
Dependent Claim
225 words
A process for fabricating a semiconductor memory device having MIS transistors composing memory cells, the memory cells having load resistors, the load resistors being connected to a power supply line, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuit being connected with a protection resistor, comprising the steps of: forming a first film of an electrically conductive material, which serves as the gate of the MIS transistors composing memory cells of the semiconductor memory device, over a semiconductor substrate, said first film having a first resistivity; forming an insulation film to cover the semiconductor substrate which is formed with each of the MIS transistors composing said memory cells; and forming second films, which second films include a layer of polycrystalline silicon, which second films respectively serve as each load resistor of each of said memory cells, as a wiring for connecting the load resistors with a power supply line and as the protection resistor connected with the gate of at least one of the MIS transistors composing peripheral circuits, over said insulation film covering said semiconductor substrate, the resistivity of the second films serving as said protection resistor and as said wiring being lower than that of the second film serving as said load resistor and higher than that of said first film.
Claim 3
Dependent Claim
39 words
A process for fabricating a semiconductor memory device according to claim 1, wherein said first film is formed by depositing polycrystalline silicon and doping the polycrystalline silicon with impurtity ions to lower the resistivity thereof to said first resistivity.
Claim 4
Dependent Claim
31 words
A process for fabricating a semiconductor memory device according to claim 1, wherein said first film is formed by depositing a metal having a high melting point, or a silicide thereof.
Claim 5
Dependent Claim
128 words
A process for fabricating a semiconductor memory device according to claim 1, wherein the forming the second films includes depositing polycrystalline silicon at the locations of each load resistor of the memory cells, at the location of the wiring for connecting the load resistors with a power supply line, and at the location of the protection resistor; masking the polycrystalline silicon at the location of each load resistor; and introducing impurtity ions into the polycrystalline silicon at the location of the wiring and protection resistor to lower the resistivity thereof, said impurity ions being introduced into the polycrystalline silicon in an amount such that the resistivity thereof is lower than that of the polycrystalline silicon serving as the load resistor but higher than that of the first film.
Claim 6
Dependent Claim
171 words
A process for fabricating a semiconductor memory device according to claim 1, wherein said protection resistor is in electrical contact with a protection diode formed in the semiconductor substrate, and wherein said process comprises the additional steps of: introducing impurity ions of a first conductivity type, opposite to that of the substrate, into the semiconductor substrate at the location at which the protection resistor is formed to contact the substrate, to form a first semiconductor region of conductivity type opposite to that of the semiconductor substrate, in the semiconductor substrate at the location at which the protection resistor is formed to contact the substrate; and introducing impurity ions of conductivity type opposite to said first conductivity type into said first semiconductor region, to form a second semiconductor region in the first semiconductor region, of conductivity type opposite to the conductivity type of the first semiconductor region; and wherein the protection resistor means is formed in contact with the second semiconductor region, the first and second semiconductor regions forming said protection diode.
Claim 7
Dependent Claim
21 words
A process for fabricating a semiconductor memory device according to claim 1, wherein all of said second films are formed simultaneously.
Claim 8
Dependent Claim
47 words
A process for fabricating a semiconductor memory device according to claim 1, wherein said forming said second films includes selectively forming a layer of polycrystalline silicon at the location for each load resistor, at the location for said wiring, and at the location for said protection resistor.
Claim 9
Dependent Claim
19 words
A process for fabricating a semiconductor memory device according to claim 2, wherein said impurity ions are phosphorus ions.
Claim 10
Dependent Claim
44 words
A process for fabricating a semiconductor memory device according to claim 7, wherein said selectively forming a layer of polycrystalline silicon includes forming a continuous layer of polycrystalline silicon over the surface of the semiconductor substrate and selectively removing portions of said continuous layer.
Claim 11
Dependent Claim
157 words
A process for fabricating a static random access memory device having MIS transistors composing memory cells, the memory cells having load resistors, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuits being connected with a protection resistor means, comprising the steps of: forming a first level conductive film over a semiconductor substrate, said first level conductive film forming the gate electrodes of the MIS transistors of the memory cells; forming an insulator film over said semiconductor substrate; and forming second level conductive films over said semiconductor substrate, said second level conductive films including a polycrystalline silicon layer, said second level conductive films being formed simultaneously at the location of said load resistors and at the location of said protection resistor means, whereby said second level conductive films to form said load resistor and at least a part of said protection resistor means are simultaneously provided.
Claim 12
Dependent Claim
157 words
A process for fabricating a static random access memory device having MIS transistors composing memory cells, the memory cells having load resistors, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuits being connected with a protection resistor means, comprising the steps of: forming a first level conductive film over a semiconductor substrate, said first level conductive film forming the gate electrodes of the MIS transistors of the memory cells; forming an insulator film over said semiconductor substrate; and forming second level conductive films over said semiconductor substrate, said second level conductive films including a polycrystalline silicon layer, said second level conductive films being formed simultaneously at the location of said load resistors and at the location of said protection resistor means, whereby said second level conductive films to form said load resistor and at least a part of said protection resistor means are simultaneously provided.
Claim 13
Dependent Claim
96 words
A process for fabricating a static random access memory device according to claim 10, wherein said first level conductive film is formed to have a first resistivity and said second level conductive films are formed to have a second resistivity, and wherein said process includes the further step of doping impurity ions into the polycrystalline silicon layer of said second level conductive films at the location of said protection resistor means to lower the resistivity thereof, to thereby form protection resistor means having a resistivity greater than said first resistivity but less than said second resistivity.
Claim 14
Dependent Claim
26 words
A process for fabricating a static random access memory device according to claim 10, wherein said second level conductive films consist of said polycrystalline silicon layer.
Claim 15
Dependent Claim
37 words
A process for fabricating a static random access memory device according to claim 10, wherein said forming said first level conductive film includes forming the first level film at the location of wiring for said peripheral circuits.
Claim 16
Dependent Claim
41 words
A process for fabricating a static random access memory device according to claim 10, wherein said first film is formed by depositing polycrystalline silicon and doping the polycrystalline silicon with impurity ions to lower the resistivity thereof to said first resistivity.
Claim 17
Dependent Claim
33 words
A process for fabricating a static random access memory device according to claim 10, wherein said first film is formed by depositing a metal having a high melting point, or a silicide thereof.
Claim 18
Dependent Claim
176 words
A process for fabricating a static random access memory device according to claim 10, wherein said protection resistor means is in electrical contact with a protection diode fomed in the semiconductor substrate, and wherein said process comprises the additional steps of: introducing impurity ions of a first conductivity type, opposite to that of the substrate, into the semiconductor substrate at the location at which the protection resistor means is formed to contact the substrate, to form a first semiconductor region, of conductivity type opposite to that of the semiconductor substrate, in the semiconductor substrate at the location at which the protection resistor means is formed to contact the substrate; and introducing impurity ions of conductivity type opposite to said first conductivity type into said first semiconductor region, to form a second semiconductor region, in the first semiconductor region, of conductivity type opposite to the conductivity type of the first semiconductor region; and wherein the protection resistor means is formed in contact with the second semiconductor region, the first and second semiconductor region forming said protection diode.
Claim 19
Dependent Claim
49 words
A process for fabricating a static random access memory device according to claim 10, wherein said forming second level conductive films includes the steps of forming a continuous film of polycrystalline silicon over said semiconductor substrate and selectively removing said continuous film to leave said second level conductive films.
Claim 20
Dependent Claim
55 words
A process for fabricating a static random access memory device according to claim 11, wherein said step of doping impurity ions includes the sub-step of forming a mask on the polycrystalline silicon layer at the location of at least said load resistors, and introducing said impurity ions selectively into the polycrystalline silicon using said mask.
Claim 21
Dependent Claim
43 words
A process for fabricating a static random access memory device according to claim 13, wherein said forming said first level conductive film includes forming the first level film at the location of the gate electrodes for the MIS transistors of the peripheral circuits.
Claim 22
Dependent Claim
21 words
A process for fabricating a static random access memory device according to claim 14, wherein said impurity ions are phosphorus ions.
Claim 23
Dependent Claim
43 words
A process for fabricating a static random access memory device according to claim 16, wherein the introducing impurity ions to form the second semiconductor region is performed after forming the first level conductive film but prior to forming the second level conductive films.
Claim 24
Dependent Claim
88 words
A process for fabricating a static random access memory device according to claim 16, wherein the step of introducing impurity ions for forming the second semiconductor region includes introducing the impurity ions into the semiconductor substrate at each side of the gate electrodes of the MIS transistors of the memory cell to form the source and drain regions for the MIS transistors of the memory cell, whereby the source and drain regions for the MIS transistors of the memory cell are formed simultaneously with said second semiconductor region.
Claim 25
Dependent Claim
85 words
A process for fabricating a static random access memory device according to claim 22, wherein the MIS transistors of the memory cell are formed in a well region of conductivity type opposite to that of the substrate, and wherein the step of introducing impurity ions for forming the first semiconductor region includes introducing impurity ions into the semiconductor substrate at a location spaced from the first semiconductor region to form said well region, whereby the well region is formed simultaneously with the first semiconductor region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-25 | 1989-05-27 | 1989-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-25 | 1993-05-27 | 1993-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-25 | 1997-05-27 | 1997-11-26 | $7700.00 | Window Closed / Lapsed |