Patent US4554645A successfully refreshed from Google Patents.
US4554645A
Expired / Lapsed
US
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Multi-port register implementation
Assignee: International Business Machines Corp
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Filing: 1983-03-10
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Granted: 1985-11-19
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Expires: 2003-03-10
Abstract
Abstract The present invention is especially directed toward a memory cell designed for use in a register stack in which multiple independent and parallel read/write and read operations may proceed simultaneously. The cell comprises multiple write transistors and multiple read transistors all coupled to a single dynamic storage means which can be written into and read from, simultaneously.
Inventors
- 👤 Anatol Furman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:39
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C7/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
108 words
A dynamic memory cell that can be concurrently written and read or sequentially written and read comprising: a write bit line transistor having its drain coupled to a first write bit line, its gate coupled to a first write word line and its source coupled to a storage means and an amplifier, said amplifier comprising a transistor whose source is grounded, whose gate is connected to the storage means and whose drain is coupled through first and second read bit line transistors to respective first and second read bit lines, the gates of the read bit line transistors being coupled to respective first and second read word lines.
Claim 2
Dependent Claim
108 words
A dynamic memory cell that can be concurrently written and read or sequentially written and read comprising: a write bit line transistor having its drain coupled to a first write bit line, its gate coupled to a first write word line and its source coupled to a storage means and an amplifier, said amplifier comprising a transistor whose source is grounded, whose gate is connected to the storage means and whose drain is coupled through first and second read bit line transistors to respective first and second read bit lines, the gates of the read bit line transistors being coupled to respective first and second read word lines.
Claim 3
Dependent Claim
12 words
The cell of claim 1 wherein said storage means comprises a capacitor.
Claim 4
Dependent Claim
46 words
The cell of claim 2 wherein said cell further includes a second write bit line transistor having its drain coupled to a second write bit line, its gate coupled to a second write word line and its source coupled to said storage means and said amplifier.
Claim 5
Dependent Claim
49 words
A memory system comprising a multiport memory cell having first and second write bit line transistors coupled between respective write bit lines and a storage means, and first and second read bit line transistors coupled between respective read bit lines and an amplifier transistor driven by said storage means.
Claim 6
Dependent Claim
49 words
A memory system comprising a multiport memory cell having first and second write bit line transistors coupled between respective write bit lines and a storage means, and first and second read bit line transistors coupled between respective read bit lines and an amplifier transistor driven by said storage means.
Claim 7
Dependent Claim
43 words
The system of claim 4 wherein each of said bit line transistors is driven by an address line decoder circuit, each write bit line is coupled to a respective write head and each read bit line is coupled to a respective read head.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |