Information storage circuit

Claim 2

In combination with a bistable circuit comprising first and second cross-coupled transistors having their collectors connected to a first point of operating potential and having their emitters connected in common to a first node, where the bistable circuit is set to one of two binary conditions by the turn on of two non-saturating transistors having their collector-to-emitter paths connected in series between the base of one of said two cross-coupled transistors and a second point of operating potential, said two non-saturating transistors, when turned on, clamping the potential between the base of said one cross-coupled transistor and said second point to V S volts, where V S is the sum of the minimum collector-to-emitter voltage drops of said two non-saturating transistors, the improvement comprising: a resistor, connected between a point common to the emitters of said two cross-coupled transistors and said second point of potential for carrying the current that flows through the two cross-coupled transistors and developing a voltage drop (V R ) across said resistor, whereby the minimum potential that must be applied between the base of said one transistor and said second point to turn on or maintain conduction of said one transistor must equal, or exceed, V R plus the base-to-emitter voltage drop (V BE ) of said one of said two cross-coupled transistors; and wherein the minimum value of said resistor is such that the sum of V R and V BE is greater than V S , and the maximum value of said resistor is such that V R plus the minimum collector-to-emitter voltage drop of either one of said two cross-coupled transistors is equal to, or less than, V S .

Claim 3

An array of memory cells sharing a common semiconductor substrate, the cells being arranged in rows and columns with a runway positioned between adjacent rows, each runway for the routing therealong of at least one of two lines across which are applied the operating potential for a row of cells, each cell including two cross-coupled transistors having their emitters connected in common to a node, means for setting each cell to one of two binary conditions including two non-saturating transistors having their collector-to-emitter paths connected in series between the base of one of said two cross-coupled transistors and a point whose potential is equal to that on said one of said two lines, the improvement comprising: a diffused region connected between said node and siad one of two lines; said diffused region providing a resistive path for conducting the current flowing through said cross-coupled transistors and producing a voltage offset raising the potential at the emitters and bases of said cross-coupled transistors, the minimum value of said resistive path being such that the voltage drop across said resistive path plus the base-to-emitter voltage drop of either one of said two cross-coupled transistors is greater than V S , where V S is equal to the sum of the minimum collector-to-emitter voltage drops of said two series connected non-saturating transistors and the maximum value of said resistive path being such that the voltage drop across said resistive path plus the minimum collector-to-emitter voltage of either one of said two cross-coupled transistors in equal to or less than V S .

Claim 4

An array of memory cells sharing a common semiconductor substrate, the cells being arranged in rows and columns with a runway positioned between adjacent rows, each runway for the routing therealong of at least one of two lines across which are applied the operating potential for a row of cells, each cell including two cross-coupled transistors having their emitters connected in common to a node, means for setting each cell to one of two binary conditions including two non-saturating transistors having their collector-to-emitter paths connected in series between the base of one of said two cross-coupled transistors and a point whose potential is equal to that on said one of said two lines, the improvement comprising: a diffused region connected between said node and siad one of two lines; said diffused region providing a resistive path for conducting the current flowing through said cross-coupled transistors and producing a voltage offset raising the potential at the emitters and bases of said cross-coupled transistors, the minimum value of said resistive path being such that the voltage drop across said resistive path plus the base-to-emitter voltage drop of either one of said two cross-coupled transistors is greater than V S , where V S is equal to the sum of the minimum collector-to-emitter voltage drops of said two series connected non-saturating transistors and the maximum value of said resistive path being such that the voltage drop across said resistive path plus the minimum collector-to-emitter voltage of either one of said two cross-coupled transistors in equal to or less than V S .

Claim 5

In a memory array in which one of two binary conditions is written on a data line by turning on a non-saturating write transistor having its collector-to-emitter path connected between said data line and a reference point, a memory cell comprising: a data input, connected to said data line, for the application thereto of binary data to be written into said memory cell; and at least one cell select terminal for the application thereto of a cell select signal for enabling the writing of data into said cell; means for the application of an operating potential between a first point and said reference point; first, second and third transistors, each transistor having emitter and collector electrodes defining the ends of a conduction path and a base electrode; means connecting the base electrode of the first transistor to the collector electrode of the second transistor and means connecting the base electrode of the second transistor to the collector electrode of the first transistor; means connecting the collector electrodes of said first and second transistors to said first point; means connecting the emitter electrodes of the first and second transistors in common to a first node; means connecting the collector-to-emitter path of said third transistor between the base electrode of said first transistor and said data input; a resistor connected between said first node and said reference point, for carrying the current that flows through said first and second transistors and developing a voltage drop (V R ) across said resistor, whereby the minimum potential differential that must be applied between the base of said first transistor and said reference point to turn it on or maintain it in conduction must equal, or exceed, V R plus the base-to-emitter voltage drop (V BE ) of said first transistor, and wherein the minimum value of said resistor is such that the sum of V R and V BE is greater than V S , where V S is defined as the sum of the minimum collector-to-emitter voltages of said third transistor and said non-saturating transistor; and said resistor having a maximum value such that V R plus the minimum collector-to-emitter voltage drop of either one of said first and second transistors is equal to, or less than, V S ; a first diode connected between a second node and the base electrode of said third transistor; a current path connected to said second node for passing a current through said first diode having a polarlity to forward bias said third transistor; and a second diode connected between said second node and said at least one cell select terminal for clamping said second node to said select terminal in the absence of a cell select signal and inhibiting the passage of said current through said first diode and thereby maintaining said third transistor in the off condition; and said second diode being reverse biased when a cell select signal is applied to said select terminal.

Claim 6

In a memory array in which one of two binary conditions is written on a data line by turning on a non-saturating write transistor having its collector-to-emitter path connected between said data line and a reference point, a memory cell comprising: a data input, connected to said data line, for the application thereto of binary data to be written into said memory cell; and at least one cell select terminal for the application thereto of a cell select signal for enabling the writing of data into said cell; means for the application of an operating potential between a first point and said reference point; first, second and third transistors, each transistor having emitter and collector electrodes defining the ends of a conduction path and a base electrode; means connecting the base electrode of the first transistor to the collector electrode of the second transistor and means connecting the base electrode of the second transistor to the collector electrode of the first transistor; means connecting the collector electrodes of said first and second transistors to said first point; means connecting the emitter electrodes of the first and second transistors in common to a first node; means connecting the collector-to-emitter path of said third transistor between the base electrode of said first transistor and said data input; a resistor connected between said first node and said reference point, for carrying the current that flows through said first and second transistors and developing a voltage drop (V R ) across said resistor, whereby the minimum potential differential that must be applied between the base of said first transistor and said reference point to turn it on or maintain it in conduction must equal, or exceed, V R plus the base-to-emitter voltage drop (V BE ) of said first transistor, and wherein the minimum value of said resistor is such that the sum of V R and V BE is greater than V S , where V S is defined as the sum of the minimum collector-to-emitter voltages of said third transistor and said non-saturating transistor; and said resistor having a maximum value such that V R plus the minimum collector-to-emitter voltage drop of either one of said first and second transistors is equal to, or less than, V S ; a first diode connected between a second node and the base electrode of said third transistor; a current path connected to said second node for passing a current through said first diode having a polarlity to forward bias said third transistor; and a second diode connected between said second node and said at least one cell select terminal for clamping said second node to said select terminal in the absence of a cell select signal and inhibiting the passage of said current through said first diode and thereby maintaining said third transistor in the off condition; and said second diode being reverse biased when a cell select signal is applied to said select terminal.

Claim 7

The memory cell as claimed in claim 3 wherein said means for passing said current includes a second resistor connected between said first point of potential and said second node.

Claim 8

The memory cell as claimed in claim 4 wherein each one of said first, second and third transistors has a diode connected between its base and its collector poled in a direction to prevent the saturation of the transistor.

Claim 9

The memory cell as claimed in claim 5 wherein said base-to-collector diode is a Schottky barrier diode; wherein said second diode is a Schottky diode; and wherein said first diode is a PN junction diode.

Claim 10

In the array as claimed in claim 6 further including an additional write transistor having its collector-to-emitter path connected between said data input and said first point for applying the other binary condition to said data input; and wherein said non-saturating write transistor has a Schottky diode connected between its base and collector.

Claim 11

The memory cell as claimed in claim 7 wherein the signal applied to said at least one cell select terminal is produced by a sixth transistor having its collector-to-emitter path connected between said terminal and said second point and a seventh transistor having its collector-to-emitter path connected between said terminal and said first point and wherein said sixth transistor has a Schottky diode connected between its base and collector.