Random access memory

Claim 2

In combination: a. means for developing a write signal; b. means, connected to the write signal developing means, for storing a binary signal in response to the write signal; c. means, connected to the storing means, for reading the binary signal stored in the storing means in response to a read signal, such reading means being connected to the storing means independently of the write signal developing means; and, d. a crystal body having a plurality of semi-conductor devices, the write signal developing means, the storing means and the reading means being integrated with the crystal body.

Claim 3

The combination recited in claim 1, wherein: the storing means is comprised of a bistable element, such bistable element storing the binary signal as a relative voltage polarity; and the reading means reads the binary signal stored by the storing means by detecting the relative voltage polarity.

Claim 4

the collector electrode of the second transistor through the diode means.

Claim 5

the collector electrode of the second transistor through the diode means.

Claim 6

The combination recited in claim 2 wherein the bistable element is comprised of: a first and second transistor, each such transistor having a first and second electrode, the first electrode of the first transistor being connected to the second electrode of the second transistor, the first electrode of the second transistor being connected to the second electrode of the first transistor.

Claim 7

The combination recited in claim 3 wherein the write signal developing means is in circuit with at least one electrode of the first trAnsistor.

Claim 8

The combination recited in claim 4 wherein the first transistor includes a third electrode and the write signal developing means is in circuit with the first electrode of the first transistor and the third electrode of the first transistor.

Claim 9

The combination recited in claim 2 wherein the bistable element is comprised of a pair of active semiconductor elements and the reading means is connected between such a pair of active semiconductor elements.

Claim 10

The combination recited in claim 3 wherein the reading means is connected to the first electrode of the first transistor and the second electrode of the first transistor.

Claim 11

The combination recited in claim 3 wherein the reading means includes a third transistor, such third transistor having at least two electrodes, one such electrode being in circuit with one electrode of the first transistor and the second electrode of the third transistor being in circuit with another electrode of the first transistor.

Claim 12

The combination recited in claim 3 wherein: the first transistor includes a third and fourth electrode and the second transistor includes a third electrode, such third electrode of the first and second transistors being connected one to the other; the write signal developing means being coupled to the third electrode; and, the binary signal being connected to the fourth electrode.

Claim 13

The combination recited in claim 9 wherein: the second transistor includes a fourth electrode; and, including means, connected to the fourth electrode of the second transistor, for providing a reference voltage on the fourth electrode of the second transistor.

Claim 14

In combination: a. a data storage element; b. means for coupling the data storage element to a write address signal source; c. means for coupling the data storage element to a read address signal source, such latter coupling means being connected to the data storage element independently of the former coupling means; and d. a crystal body having a plurality of semiconductor devices, the data storage element, the write address signal source coupling means, and the read address signal source coupling means being integrated with the coupling means being integrated with the crystal body.

Claim 15

In combination: a. a data storage element; b. means for coupling the data storage element to a write address signal source; c. means for coupling the data storage element to a read address signal source, such latter coupling means being connected to the data storage element independently of the former coupling means; and d. a crystal body having a plurality of semiconductor devices, the data storage element, the write address signal source coupling means, and the read address signal source coupling means being integrated with the coupling means being integrated with the crystal body.

Claim 16

The combination recited in claim 11 wherein the data storage element is comprised of a pair of transistors, the base electrode and the collector electrode of one of the pair of transistors being connected respectively to the collector electrode and the base electrode of the other one of the pair of transistors.

Claim 17

The combination recited in claim 12 wherein the read addressing signal source coupling means is coupled to the base electrode and the collector electrode of one of the pair of transistors.

Claim 18

In combination: a. a plurality of data storage elements, such elements being adapted to have data applied thereto, a group of selected ones thereof storing data applied thereto in response to a write addressing signal applied to each one of the data storage elements of the group; b. a plurality of reading means, each one thereof being coupled to a different one of the plurality of data storage elements and being responsive to a read addressing signal applied to each one of a group of selected ones of the reading means, such reading means being connected to the storage element independently of the write addressing signal, for sensing the data stored in the data storage elements coupled thereto in response to the read addressing signal; and c. a crystal body having a plurality of semiconductor devices, the plurality of storage means and the plurality of reading means being integrated with the crystal body.

Claim 19

In combination: a. a plurality of data storage elements, such elements being adapted to have data applied thereto, a group of selected ones thereof storing data applied thereto in response to a write addressing signal applied to each one of the data storage elements of the group; b. a plurality of reading means, each one thereof being coupled to a different one of the plurality of data storage elements and being responsive to a read addressing signal applied to each one of a group of selected ones of the reading means, such reading means being connected to the storage element independently of the write addressing signal, for sensing the data stored in the data storage elements coupled thereto in response to the read addressing signal; and c. a crystal body having a plurality of semiconductor devices, the plurality of storage means and the plurality of reading means being integrated with the crystal body.

Claim 20

The combination recited in claim 14 wherein each one of the plurality of data storage elements is comprised of a pair of transistors, the base electrode and the collector electrode of one of the pair of transistors being directly connected respectively to the collector electrode and the base electrode of the other onE of such pair of transistors.

Claim 21

The combination recited in claim 15 wherein each one of the plurality of reading means is coupled to the base electrode and the collector electrode of one of the pair of transistors.

Claim 22

In combination: a. a plurality of data storage elements; b. means for applying data to be stored in each one of such plurality of data storage elements; c. writing means for enabling selected ones of such data storage elements to store data applied thereto; a plurality of reading means, each one thereof being coupled to a different one of the plurality of data storage elements, for sensing the data stored in selected ones of the plurality of storage elements, such reading means being connected to the storage element independently of the writing means; and e. a crystal body having a plurality of semiconductor devices, the plurality of data storage elements, the data applying means, the writing means and the reading means being integrated with the crystal body.

Claim 23

In combination: a. a plurality of data storage elements; b. means for applying data to be stored in each one of such plurality of data storage elements; c. writing means for enabling selected ones of such data storage elements to store data applied thereto; a plurality of reading means, each one thereof being coupled to a different one of the plurality of data storage elements, for sensing the data stored in selected ones of the plurality of storage elements, such reading means being connected to the storage element independently of the writing means; and e. a crystal body having a plurality of semiconductor devices, the plurality of data storage elements, the data applying means, the writing means and the reading means being integrated with the crystal body.

Claim 24

The combination recited in claim 17 wherein each one of the plurality of data storage elements is comprised of a pair of transistors, the base electrode and the collector electrode of such pair of transistors being directly connected respectively to the collector electrode and the base electrode of the other one of such pair of transistors.

Claim 25

The combination recited in claim 18 wherein each one of the plurality of reading means is coupled to the base electrode and the collector electrode of one of the pair of transistors of the data storage element coupled to such one of the reading means.

Claim 26

A storage cell comprising: a. a means for receiving a binary signal; b. a directly coupled bistable multivibrator connected to the receiving means; c. write enable means for coupling the directly coupled bistable multivibrator to a write enable signal and for enabling the binary signal on the receiving means to be stored in such multivibrator in response to the write enable signal; d. sensing means, operative independently of the write enable means and responsive to a read enable signal, for sensing the binary signal stored in such multivibrator in response to the read enable signal; e. a data output means for receiving the binary signal sensed in the multivibrator in response to the read enable signal; and f. a crystal body having a plurality of semiconductor devices, the receiving means, the directly coupled bistable multi-vibrator, the write enable means, the sensing means and the data output means being integrated with the crystal body.

Claim 27

A storage cell comprising: a. a means for receiving a binary signal; b. a directly coupled bistable multivibrator connected to the receiving means; c. write enable means for coupling the directly coupled bistable multivibrator to a write enable signal and for enabling the binary signal on the receiving means to be stored in such multivibrator in response to the write enable signal; d. sensing means, operative independently of the write enable means and responsive to a read enable signal, for sensing the binary signal stored in such multivibrator in response to the read enable signal; e. a data output means for receiving the binary signal sensed in the multivibrator in response to the read enable signal; and f. a crystal body having a plurality of semiconductor devices, the receiving means, the directly coupled bistable multi-vibrator, the write enable means, the sensing means and the data output means being integrated with the crystal body.

Claim 28

In combination: a. a plurality of storage means arranged in a matrix, each one thereof including: i. a data input means for receiving a binary signal; ii. write means for coupling the storage means to a write signal, and for enabling the binary signal on the data input means to be stored in the storage means in response to such write enable signal; iii. sensing means, operative independently of the write enable means and responsive to a read signal, for sensing the binary signal stored in the storage means in response to such read signal; b. means for applying a write signal to selected ones of the write means; c. means for applying a read signal to selected ones of the sensing means; and d. a crystal body having a plurality of semiconductor devices, the plurality of storage means, the write signal applying means and the read signal applying means being integrated with the crystal body.

Claim 29

In combination: a. a plurality of storage means arranged in a matrix, each one thereof including: i. a data input means for receiving a binary signal; ii. write means for coupling the storage means to a write signal, and for enabling the binary signal on the data input means to be stored in the storage means in response to such write enable signal; iii. sensing means, operative independently of the write enable means and responsive to a read signal, for sensing the binary signal stored in the storage means in response to such read signal; b. means for applying a write signal to selected ones of the write means; c. means for applying a read signal to selected ones of the sensing means; and d. a crystal body having a plurality of semiconductor devices, the plurality of storage means, the write signal applying means and the read signal applying means being integrated with the crystal body.

Claim 30

A storage cell comprising: a. a first and second transistor arranged as a bistable multivibrator, each one of such transistors having a data emitter electrode a write enable emitter electrode, a base electrode and a collector electrode, the base electrode and collector electrode of one of such transistors being directly connected to the collector electrode and base electrode of the other one of such transistors, respectively; b. a voltage reference means connectEd to the data emitter electrode of the first transistor; c. a data line connected to the data emitter electrode of the second transistor; d. a write enable line connected to the write enable emitter electrode of the first and the second transistor; e. a reading means connected to the collector electrode of the first and the second transistor, such reading means including: i. a diode means; and, ii. a transistor, such transistor having its emitter electrode connected to the collector electrode of the first transistor and a base electrode connected to:

Claim 31

A storage cell comprising: a. a first and second transistor arranged as a bistable multivibrator, each one of such transistors having a data emitter electrode a write enable emitter electrode, a base electrode and a collector electrode, the base electrode and collector electrode of one of such transistors being directly connected to the collector electrode and base electrode of the other one of such transistors, respectively; b. a voltage reference means connectEd to the data emitter electrode of the first transistor; c. a data line connected to the data emitter electrode of the second transistor; d. a write enable line connected to the write enable emitter electrode of the first and the second transistor; e. a reading means connected to the collector electrode of the first and the second transistor, such reading means including: i. a diode means; and, ii. a transistor, such transistor having its emitter electrode connected to the collector electrode of the first transistor and a base electrode connected to: