US3704455A
Expired / Lapsed
US
⏱️ 0.0 years remaining
3d-coaxial memory construction and method of making
Assignee: Contel Federal Systems Inc
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Filing: 1971-02-01
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Granted: 1972-11-28
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Expires: 1991-02-01
Abstract
Abstract A semiconductor memory in which integrated circuit chips each containing semiconductor flip-flop memory elements are mounted to respective ones of a plurality of batch-fabricated, pressurestacked electrically conductive wafers so as to form a compact, essentially all metal, three-dimensional memory structure. Coaxially-shielded X, Y and Z conductors are formed in the conductive wafers ny selective chemical etching for expeditiously providing the interconnections required for the integrated circuit chips in accordance with the desired memory organization.
Inventors
- 👤 Alfred D Scarbrough
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W90/401; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
219 words
In a construction for a digital memory, the combination comprising: a plurality of pressure-stacked electrically conductive wafers forming a three-dimensional stack having X, Y and Z-axes with the wafers being in the X-Y planes and being stacked in the Zaxis direction, each wafer having a plurality of Z-axis terminals provided in respective openings in the wafer in a manner so as to be insulated therefrom and from each other, at least predetermined ones of said Z-axis terminals being through-terminals which are respectively aligned on the wafers so as to form insulated Zaxis paths within the stack traversing the wafers thereof, malleable conductive means provided between adjacent wafers for respectively connecting aligned Z-axis terminals on adjacent wafers, a plurality of memory element chips mounted to said wafers with at least predetermined ones of said wafers having a plurality of chips mounted thereto, each chip having a plurality of output leads, said digital memory having an organization such that a majority of the output leads of each chip require respective common connection with corresponding leads of a plurality of other chips on a plurality of different wafers, and means connecting said majority of output leads of the chips to respectively aligned Z-axis through-terminals of their respective wafers so that predetermined ones of said Z-axis paths provide said required respective common connections.
Claim 2
Dependent Claim
219 words
In a construction for a digital memory, the combination comprising: a plurality of pressure-stacked electrically conductive wafers forming a three-dimensional stack having X, Y and Z-axes with the wafers being in the X-Y planes and being stacked in the Zaxis direction, each wafer having a plurality of Z-axis terminals provided in respective openings in the wafer in a manner so as to be insulated therefrom and from each other, at least predetermined ones of said Z-axis terminals being through-terminals which are respectively aligned on the wafers so as to form insulated Zaxis paths within the stack traversing the wafers thereof, malleable conductive means provided between adjacent wafers for respectively connecting aligned Z-axis terminals on adjacent wafers, a plurality of memory element chips mounted to said wafers with at least predetermined ones of said wafers having a plurality of chips mounted thereto, each chip having a plurality of output leads, said digital memory having an organization such that a majority of the output leads of each chip require respective common connection with corresponding leads of a plurality of other chips on a plurality of different wafers, and means connecting said majority of output leads of the chips to respectively aligned Z-axis through-terminals of their respective wafers so that predetermined ones of said Z-axis paths provide said required respective common connections.
Claim 3
Dependent Claim
44 words
The invention in accordance with claim 1, wherein each chip contains a plurality of bistable semiconductor memory elements and decoder means for selecting a particular bistable element for a read or a write operation in response to signals applied to chip address output leads.
Claim 4
Dependent Claim
19 words
The invention in accordance with claim 2, wherein said majority of output leads include said chip address output leads.
Claim 5
Dependent Claim
34 words
The invention in accordance with claim 1, wherein said malleable conductive means additionally provide for electrically connecting adjacent conductive wafer surfaces so that each of said Z-axis paths is coaxially shielded throughout its length.
Claim 6
Dependent Claim
35 words
The invention in accordance with claim 4, wherein chips whose majority of output leads are to be respectively commonly connected are located on their respective wafers so as to be aligned in the Z-axis direction.
Claim 7
Dependent Claim
62 words
The invention in accordance with claim 1, wherein predetermined ones of said wafers are additionally provided with insulated X-Y conductors interconnecting predetermined ones of their respective Z-axis terminals, each X-Y conductor being provided within a respective opening of its respective wafer in a manner so as to be insulated therefrom and from said Z-axis terminals as well as from other X-Y conductors.
Claim 8
Dependent Claim
47 words
The invention in accordance with claim 6, wherein each X-Y conductor is recessed from the surfaces of its respective wafer, and wherein the wafers adjacent each X-Y conductor combine with the shielding provided by the surrounding portions of its respective wafer to provide complete electrical shielding therefor.
Claim 9
Dependent Claim
33 words
The invention in accordance with claim 7, wherein said malleable conductive means additionally provide for electrically connecting adjacent wafer surfaces so that each of said Z-axis paths is coaxially shielded throughout its length.
Claim 10
Dependent Claim
65 words
The invention in accordance with claim 8, wherein the organization of said memory is also such That a common connection is required between at least one predetermined chip output lead of a plurality of chips on the same wafer, and wherein a predetermined X-Y conductor is provided on a predetermined wafer in order to provide this required common connection between said predetermined chip output leads.
Claim 11
Dependent Claim
100 words
The invention in accordance with claim 8, wherein the organization of said memory is further such as to require that the common connection of said predetermined chip output leads of chips on the same wafer not be connected to chip output leads of chips on other wafers, wherein the Z-axis terminals to which said predetermined chip output leads are connected are accordingly not provided as through-terminals, and wherein said predetermined X-Y conductor is connected to a free Z-axis through-terminal on its respective wafer so as to extend to at least one end of the stack via a respective Z-axis path.
Claim 12
Dependent Claim
40 words
The invention in accordance with claim 10, wherein said wafers comprise an alternating arrangement of memory chip wafers and interconnection wafers, and wherein said chips are provided only on said memory chip wafers and in a like arrangement on each.
Claim 13
Dependent Claim
47 words
The invention in accordance with claim 11, wherein each of said interconnection wafers serves to provide appropriate memory chip recesses and spacing for a respective adjacent memory chip wafer, and wherein each of said interconnection wafers contains at least one X-Y conductor connecting predetermined Z-axis terminals thereof.
Claim 14
Dependent Claim
113 words
The invention in accordance with claim 12, wherein said majority of output leads of each chip are connected to respective Z-axis through-terminals of its respective wafer, wherein said predetermined output lead of each chip is connected to a respective Z-axis terminal of its respective wafer which is not a through-terminal but is constructed so as to only make contact with the particular aligned Z-axis terminal of its respective adjacent interconnection wafer, and wherein an X-Y conductor is provided on each adjacent interconnection wafer requiring same for commonly connecting said particular aligned Z-axis terminals thereof so as to provide the required common connections of said predetermined output leads for its respective memory chip wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-11-28 | 1976-05-29 | 1976-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-11-28 | 1980-05-29 | 1980-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-11-28 | 1984-05-29 | 1984-11-28 | $7700.00 | Window Closed / Lapsed |