Patent US4551638A successfully refreshed from Google Patents.
US4551638A
Expired / Lapsed
US
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ECL Gate with switched load current source
Assignee: RPX Corp
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Filing: 1983-12-19
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Granted: 1985-11-05
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Expires: 2003-12-19
Abstract
Abstract A standard ECL OR/NOR gate is modified to have a single current source connected to the load current source transistors. The single current source is connected to the emitters of each of the load current source transistors. Switching between the two load current source transistors is accomplished by connecting the base of at least one of the load current transistors to a circuit point that tracks the opposite phase. In one embodiment the base of one of the load current source transistors is connected to the common emitter connections of the input transistors and the reference transistor while the base of the other load current source transistor is connected to a reference voltage source V BBL having a value intermediate the extreme values which appear on the common emitter connections of the input transistors and the reference transistors. In an alternate embodiment the base of each load current source transistor is connected to a suitable point which tracks the opposite phase outputs of the particular load current source transistor.
Inventors
- 👤 Hemmige D. Varadarajan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/001; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0866
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
336 words
An emitter coupled logic gate having a true output and a complementary output, comprising: a reference transistor having a base connected to a switch reference voltage supply line, a collector connected through a first collector resistor to a V CC voltage supply line, and an emitter connected to a first common emitter node; at least one input transistor, each having a base connected to a respective input node, a collector connected at a common collector node and through a second collector resistor to the V CC voltage supply line, and an emitter connected to the first common emitter node; a first emitter follower transistor having a base connected to the collector of said reference transistor, a collector connected to the V CC voltage supply line, and an emitter connected to an output line supplying one output of the true or complementary outputs; a second emitter follower transistor having a base connected to the common collector node of said at least one input transistor, a collector connected to the V CC voltage supply line, and an emitter connected to an output line supplying the other output of the true or complementary outputs; a main current source supplying a gate current at the first common emitter node; a first load current source transistor having a base connected to a circuit node which experiences a voltage swing as the gate switches, a collector connected to the output line supplying said one output and an emitter connected to a second common emitter node, said voltage swing being out-of-shape with said one output as the gate switches; a second load current source transistor having a base connected to a reference node suppling a load reference voltage, a collector connected to the output line supplying said other output, and an emitter connected to said second common emitter node; a load current source supplying a load current at said second common emitter node; and a resistor connected between the output line supplying said one output and the output line supplying said other output.
Claim 2
Dependent Claim
336 words
An emitter coupled logic gate having a true output and a complementary output, comprising: a reference transistor having a base connected to a switch reference voltage supply line, a collector connected through a first collector resistor to a V CC voltage supply line, and an emitter connected to a first common emitter node; at least one input transistor, each having a base connected to a respective input node, a collector connected at a common collector node and through a second collector resistor to the V CC voltage supply line, and an emitter connected to the first common emitter node; a first emitter follower transistor having a base connected to the collector of said reference transistor, a collector connected to the V CC voltage supply line, and an emitter connected to an output line supplying one output of the true or complementary outputs; a second emitter follower transistor having a base connected to the common collector node of said at least one input transistor, a collector connected to the V CC voltage supply line, and an emitter connected to an output line supplying the other output of the true or complementary outputs; a main current source supplying a gate current at the first common emitter node; a first load current source transistor having a base connected to a circuit node which experiences a voltage swing as the gate switches, a collector connected to the output line supplying said one output and an emitter connected to a second common emitter node, said voltage swing being out-of-shape with said one output as the gate switches; a second load current source transistor having a base connected to a reference node suppling a load reference voltage, a collector connected to the output line supplying said other output, and an emitter connected to said second common emitter node; a load current source supplying a load current at said second common emitter node; and a resistor connected between the output line supplying said one output and the output line supplying said other output.
Claim 3
Dependent Claim
51 words
The emitter coupled logic gate of claim 1, wherein: said logic gate has a logic swing voltage defining a difference between the true and complementary outputs when the gate is not switching; and said resistor has a resistance value given approximately by the logic swing voltage divided by the load current.
Claim 4
Dependent Claim
31 words
The emitter coupled logic gate of claim 2, wherein: said circuit node is said first common emitter node, and said reference node is connected to a load reference voltage supply line.
Claim 5
Dependent Claim
74 words
The emitter coupled logic gate of claim 1, wherein: said resistor includes a first resistor connected between the output line supplying said one output and a first node, a second resistor connected between said first node and a second node, and a third resistor connected between the output line supplying said other output and said second node; and wherein said circuit node is said second node; and said reference node is said first node.
Claim 6
Dependent Claim
152 words
The emitter coupled logic gate of claim 1, further including: a second series of input transistors having their emitters coupled to said common collector node and their collectors connected to a second common collector node and through said second collector resistor to the V CC voltage supply line; a second reference transistor having a base connected to a second switch reference voltage supply line, a collector connected through said first collector resistor to the V CC voltage supply line and an emitter connected to said common collector node in common with the emitters of said second series of input transistors; and a diode coupled between the emitter of said first emitter follower transistor and said output line supplying one output of the true or complementary outputs; and a diode connected between the emitter of second emitter follower transistor and said output line supplying the other output of the true or complementary outputs.
Claim 7
Dependent Claim
29 words
The emitter coupled logic gate of claim 1 wherein said load reference voltage has a value midway between said extreme values of the voltages experienced on said circuit node.
Claim 8
Dependent Claim
48 words
The emitter coupled logic gate of claim 2 wherein the value of said load reference voltage is given approximately by: V.sub.BB -V.sub.BE +(V.sub.SW /4) where V BB =said switch reference voltage V BE =base-to-emitter voltage drop of said at least one input transistor V SW =logic swing voltage.
Claim 9
Dependent Claim
20 words
The emitter coupled logic gate of claim 4 wherein said first resistor and said second resistor have approximately equal values.
Claim 10
Dependent Claim
54 words
The emitter coupled logic gate of claim 6, 5, 8, 1, 2, 3, 4, or 5, wherein said load current source comprises a transistor having an emitter coupled to a V EE voltage supply line, a collector connected to said second common emitter node and a base connected to a bandgap reference voltage generator.
Claim 11
Dependent Claim
46 words
The emitter coupled logic gate of claim 9 wherein said main current source comprises a transistor having an emitter coupled to the V EE voltage supply line, a collector connected to said first common emitter node, and a base, connected to said bandgap reference voltage generator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-04 | 1989-05-06 | 1989-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-04 | 1993-05-06 | 1993-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-04 | 1997-05-06 | 1997-11-05 | $7700.00 | Window Closed / Lapsed |