Patent US4547957A successfully refreshed from Google Patents.
US4547957A
Expired / Lapsed
US
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Imaging device having improved high temperature performance
Assignee: Burle Technologies Inc
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Filing: 1984-08-01
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Granted: 1985-10-22
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Expires: 2004-08-01
Abstract
Abstract An imaging device includes a wafer of single crystal semiconductor material having a first surface with an input surfacing region which extends into the wafer from the first surface and a second surface with a charge storage portion which includes a plurality of discrete charge storing regions which extend into the wafer of the second surface. The wafer includes a potential barrier within the input signal sensing portion for controlling blooming. The wafer is improved by including a passivation region within the input sensing portion for stabilizing the energy level of the conductivity band of the minority carriers at the Fermi energy level of the semiconductor wafer. Additionally, an electrical leakage reduction region extends into the wafer from the second surface. The leakage reduction region is contiguous with each of the discrete charge storage regions.
Inventors
- 👤 Eugene D. Savoye
- 👤 Charles M. Tomasetti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:17
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/011; H10F39/028; H10F39/026; H10F39/10; H10F39/12; H10F39/18; H10F39/186; Y; Y10; Y10S; Y10S148/00; Y10S148/024; Y10S148/06; Y10S148/172
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
290 words
A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a first type conductivity, said wafer having first and second major surfaces; forming a capping oxide on at least said second major surface of said wafer; introducing an element through said capping oxide into said second major surface of said wafer so as to form a region of enhanced first type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said wafer; forming an insulating layer on said second major surface of said wafer; providing a plurality of apertures through said insulating layer; forming a plurality of regions of a second type conductivity through said apertures, said second type conductivity regions extending into said wafer from said second surface a distance greater than said region of enhanced first type conductivity; introducing an element into said first major surface of said wafer so as to form a region of enhanced first type conductivity for controlling blooming, said region being spaced from said first major surface; activating said introduced element by heating said wafer at an elevated temperature; and forming a shallow region of a second type conductivity extending into said wafer from said first major surface for a distance less than said region of enhanced first type conductivity for controlling blooming, said shallow region of second type conductivity and said region of enhanced first type conductivity for controlling blooming acting in combination to prevent minority carriers from localized sites on the first major surface of the wafer from reaching said regions of second type conductivity extending into said wafer from the second major surface thereof.
Claim 2
Independent Claim
290 words
A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a first type conductivity, said wafer having first and second major surfaces; forming a capping oxide on at least said second major surface of said wafer; introducing an element through said capping oxide into said second major surface of said wafer so as to form a region of enhanced first type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said wafer; forming an insulating layer on said second major surface of said wafer; providing a plurality of apertures through said insulating layer; forming a plurality of regions of a second type conductivity through said apertures, said second type conductivity regions extending into said wafer from said second surface a distance greater than said region of enhanced first type conductivity; introducing an element into said first major surface of said wafer so as to form a region of enhanced first type conductivity for controlling blooming, said region being spaced from said first major surface; activating said introduced element by heating said wafer at an elevated temperature; and forming a shallow region of a second type conductivity extending into said wafer from said first major surface for a distance less than said region of enhanced first type conductivity for controlling blooming, said shallow region of second type conductivity and said region of enhanced first type conductivity for controlling blooming acting in combination to prevent minority carriers from localized sites on the first major surface of the wafer from reaching said regions of second type conductivity extending into said wafer from the second major surface thereof.
Claim 3
Independent Claim
299 words
A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a N- type conductivity, said wafer having first and second major surfaces; growing a capping oxide having a thickness of about 300 Å on said second major surface of said wafer; implanting through said capping oxide an element selected from the group consisting of phosphorous and arsenic into said second surface of said wafer so as to form a region of N+ type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said second major surface of said wafer; forming an insulating layer on said second major surface of said wafer; etching a plurality of apertures through said insulating layer; forming a plurality of regions of a P- type conductivity through said apertures, said P- type conductivity regions extending into said wafer from said second major surface a distance greater than said region of N+ type conductivity; implanting arsenic into said first major surface of said wafer so as to form a potential barrier comprising a region of N+ type conductivity for controlling blooming, said region being spaced from said first major surface; annealing said wafer to activate said arsenic atoms implanted into said first major surface; and forming a shallow region of P- type conductivity extending into said wafer from said first major surface for a distance less than said potential barrier, said shallow region of P- type conductivity and said potential barrier acting in combination to prevent holes from localized sites on the first major surface of the wafer from overcoming the potential barrier and reaching the P- type conductivity regions extending into said wafer from the second major surface thereof.
Claim 4
Independent Claim
299 words
A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a N- type conductivity, said wafer having first and second major surfaces; growing a capping oxide having a thickness of about 300 Å on said second major surface of said wafer; implanting through said capping oxide an element selected from the group consisting of phosphorous and arsenic into said second surface of said wafer so as to form a region of N+ type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said second major surface of said wafer; forming an insulating layer on said second major surface of said wafer; etching a plurality of apertures through said insulating layer; forming a plurality of regions of a P- type conductivity through said apertures, said P- type conductivity regions extending into said wafer from said second major surface a distance greater than said region of N+ type conductivity; implanting arsenic into said first major surface of said wafer so as to form a potential barrier comprising a region of N+ type conductivity for controlling blooming, said region being spaced from said first major surface; annealing said wafer to activate said arsenic atoms implanted into said first major surface; and forming a shallow region of P- type conductivity extending into said wafer from said first major surface for a distance less than said potential barrier, said shallow region of P- type conductivity and said potential barrier acting in combination to prevent holes from localized sites on the first major surface of the wafer from overcoming the potential barrier and reaching the P- type conductivity regions extending into said wafer from the second major surface thereof.
Claim 5
Dependent Claim
33 words
The method as in claim 2, wherein the element implanted through said capping oxide has an implant energy of about 175 KeV and a dosage of approximately 1.0×10 12 atoms per square centimeter.
Claim 6
Dependent Claim
21 words
The method as in claim 3, wherein phosphorous extends into said wafer about 18,000 to 20,000 Å from said second surface.
Claim 7
Dependent Claim
19 words
The method as in claim 3, wherein arsenic extends into said wafer about 2,000 Å from said second surface.
Claim 8
Dependent Claim
39 words
The method as in claim 2, wherein said arsenic implanted into said first surface of said wafer for controlling blooming has an implant energy of about 70 KeV and a dosage of approximately 1.2×10 13 atoms per square centimeter.
Claim 9
Dependent Claim
47 words
The method as in claim 2, wherein about 1.1×10 20 boron atoms per cubic centimeters are diffused into the first surface at a temperature of about 875° C. for about 5 minutes to provide a second type conductivity region extending into said wafer for about 500 Å.
Claim 10
Dependent Claim
62 words
The method as in claim 6, wherein boron fluoride is implanted into said first surface of said wafer at an implant energy of 5 KeV at a dosage ranging from about 7×10 13 to about 7×10 14 atoms per square centimeter, said wafer being annealed at a temperature of about 850° C. for 45 minutes following the implantation of said boron fluoride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-21 | 1989-04-22 | 1989-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-21 | 1993-04-22 | 1993-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-21 | 1997-04-22 | 1997-10-22 | $7700.00 | Window Closed / Lapsed |