US3676727A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Diode-array target including isolating low resistivity regions
Assignee: AT&T Inc
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Filing: 1970-03-30
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Granted: 1972-07-11
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Expires: 1990-03-30
Abstract
Abstract The specification describes an improved diode array target for an electron beam storage tube. The target is an improvement of the device described in U.S. Pat. Nos. 3,403,284 and 3,419,746. The target is modified so as to include an N layer in the surface region of the semiconductor substrate between the diodes. This layer serves to isolate the diodes, to reduce the dark current generation, and to increase the resolution of the camera tube.
Inventors
- 👤 John Vincent Dalton
- 👤 Edward Franklin Labuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:50
CPC Classifications
H; H01; H01J; H01J29/00; H01J29/02; H01J29/10; H01J29/36; H01J29/39; H01J29/45; H01J29/451; H01J29/453; H01J29/455; H10; H10D; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/061; Y10S148/072
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
149 words
An electron beam storage device comprising in combination: a target structure comprising an n-type silicon wafer having a resistivity in the range of 1 ohm cm to 100 ohm cm; an array of p-type impurity regions formed into a surface of the wafer, each of said regions forming with the major portion of the wafer a p-n junction, an SiO2 dielectric layer covering the n-type portion of the surface around the p-type regions, means for scanning the array of p-n junctions with the electron beam, and an n-type impurity region formed into the surface of the wafer between the array of p-type impurity regions so as to surround each of the pn junctions annularly, said region having a resistivity significantly less than the resistivity of the remaining n-type portion of the wafer and an impurity concentration of at least 1016 atoms/cc. and extending through the thickness of the wafer.
Claim 2
Dependent Claim
149 words
An electron beam storage device comprising in combination: a target structure comprising an n-type silicon wafer having a resistivity in the range of 1 ohm cm to 100 ohm cm; an array of p-type impurity regions formed into a surface of the wafer, each of said regions forming with the major portion of the wafer a p-n junction, an SiO2 dielectric layer covering the n-type portion of the surface around the p-type regions, means for scanning the array of p-n junctions with the electron beam, and an n-type impurity region formed into the surface of the wafer between the array of p-type impurity regions so as to surround each of the pn junctions annularly, said region having a resistivity significantly less than the resistivity of the remaining n-type portion of the wafer and an impurity concentration of at least 1016 atoms/cc. and extending through the thickness of the wafer.
Claim 3
Dependent Claim
24 words
The storage device of claim 1 in which the impurity regions and the dielectric layer are covered with 500 to 10,000 A. of Sb2S3.
Claim 4
Dependent Claim
21 words
The storage device of claim 1 in which the impurity regions are covered with 200 to 1,500 A. of gallium arsenide.
Claim 5
Dependent Claim
15 words
The storage device of claim 1 further including metal conducting islands covering each impurity region.
Claim 6
Dependent Claim
19 words
The storage device of claim 4 in which the metal conductive islands comprise 0.1 to 1.0 Mu of gold.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-11 | 1976-01-10 | 1976-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-11 | 1980-01-10 | 1980-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-11 | 1984-01-10 | 1984-07-11 | $7700.00 | Window Closed / Lapsed |