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US3828232A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor target

Assignee: Toshiba Corp
•
Filing: 1973-02-28
•
Granted: 1974-08-06
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Expires: 1993-02-28
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Abstract

Abstract A semiconductor target comprises a semiconductor substrate and a diode array patterned on the substrate. Diodes are isolated from each other by an insulating film. A p-n junction plane of the diodes is designed to lie over the boundary plane of the substrate and the insulating film.

Inventors

  • 👤 Y Horiike
  • 👤 S Shirouzu
  • 👤 S Tsuji
  • 👤 N Harada

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 01:30
CPC Classifications
H; H10; H10P; H10P95/00; H01; H01J; H01J29/00; H01J29/02; H01J29/10; H01J29/36; H01J29/39; H01J29/45; H01J29/451; H01J29/453; H01J29/455; H01J9/00; H01J9/20; H01J9/233; H10D; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/006; Y10S148/026; Y10S148/05; Y10S148/12; Y10S257/00; Y10S257/917

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 149 words
A semiconductor target comprising: a semiconductor substrate having one type of conductivity; an insulating layer in contact with and on a major surface of said substrate and which is provided with a plurality of holes; a first semiconductor region in said holes in contact with said substrate and having the same conductivity type as that of said substrate and a different impurity density from that of said substrate; a second semiconductor region in contact with said first semiconductor region and having an opposite type of conductivity as that of said substrate, wherein said boundary plane between said semiconductor substrate and said insulating layer and a boundary plane between said semiconductor region and said semiconductor substrate line in a same plane; wherein a p-n junction between said first and second semiconductor regions is formed over a plane which forms a boundary plane between said semiconductor substrate and said insulating film.
Claim 2
Dependent Claim 149 words
A semiconductor target comprising: a semiconductor substrate having one type of conductivity; an insulating layer in contact with and on a major surface of said substrate and which is provided with a plurality of holes; a first semiconductor region in said holes in contact with said substrate and having the same conductivity type as that of said substrate and a different impurity density from that of said substrate; a second semiconductor region in contact with said first semiconductor region and having an opposite type of conductivity as that of said substrate, wherein said boundary plane between said semiconductor substrate and said insulating layer and a boundary plane between said semiconductor region and said semiconductor substrate line in a same plane; wherein a p-n junction between said first and second semiconductor regions is formed over a plane which forms a boundary plane between said semiconductor substrate and said insulating film.
Claim 3
Dependent Claim 23 words
A semiconductor target according to claim 1, wherein an impurity density of said substrate is lighter than that of said first semiconductor region.
Claim 4
Dependent Claim 30 words
A semiconductor target according to claim 2 wherein said substrate includes impurity density means to prevent a formation of an inverted layer caused by a charge on said insulating layer.
Claim 5
Dependent Claim 45 words
A semiconductor target according to claim 1, wherein a third semiconductor with the same type conductivity as the semiconductor substrate is formed on a surface of the semiconductor substrate which is opposite a surface of the semiconductor substrate having the insulating layer in contact therewith.
Claim 6
Dependent Claim 134 words
A semiconductor target comprising: a semiconductor substrate having one type of conductivity; an insulating layer in contact with and on a major surface of said substrate and which is provided with a plurality of holes; a first semiconductor region in said holes in contact with said substrate and having the same conductivity type as that of said substrate and a different impurity density from that of said substrate; a second semiconductor region in contact with said first semiconductor region and having an opposite type of conductivity as that of said substrate, wherein a portion of said first semiconductor region is disposed beneath said insulating layer; whereby a p-n junction between the first and second semiconductor regions is formeD over a plane which forms a boundary plane between said semiconductor substrate and said insulating layer.
Claim 7
Dependent Claim 134 words
A semiconductor target comprising: a semiconductor substrate having one type of conductivity; an insulating layer in contact with and on a major surface of said substrate and which is provided with a plurality of holes; a first semiconductor region in said holes in contact with said substrate and having the same conductivity type as that of said substrate and a different impurity density from that of said substrate; a second semiconductor region in contact with said first semiconductor region and having an opposite type of conductivity as that of said substrate, wherein a portion of said first semiconductor region is disposed beneath said insulating layer; whereby a p-n junction between the first and second semiconductor regions is formeD over a plane which forms a boundary plane between said semiconductor substrate and said insulating layer.
Claim 8
Dependent Claim 24 words
A semiconductor target according to claim 5, wherein an impurity density of said first semiconductor region is heavier than that of said semiconductor substrate.
Claim 9
Dependent Claim 28 words
A semiconductor target according to claim 6, wherein said impurity density and the width of said first semiconductor region form a wide depletion layer in said semiconductor substrate.

References Cited (Backward Citations)

US3386865A Cited
US3534234A Cited
US3649889A Cited
US3737702A Cited
US3707657A Cited
US3611058A Cited
US3648125A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-08-05 1978-02-04 1978-08-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-08-05 1982-02-04 1982-08-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-08-05 1986-02-04 1986-08-06 $7700.00 Window Closed / Lapsed

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