Imaging device having improved high temperature performance

Claim 1

A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a first type conductivity, said wafer having first and second major surfaces; forming a capping oxide on at least said second major surface of said wafer; introducing an element through said capping oxide into said second major surface of said wafer so as to form a region of enhanced first type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said wafer; forming an insulating layer on said second major surface of said wafer; providing a plurality of apertures through said insulating layer; forming a plurality of regions of a second type conductivity through said apertures, said second type conductivity regions extending into said wafer from said second surface a distance greater than said region of enhanced first type conductivity; introducing an element into said first major surface of said wafer so as to form a region of enhanced first type conductivity for controlling blooming, said region being spaced from said first major surface; activating said introduced element by heating said wafer at an elevated temperature; and forming a shallow region of a second type conductivity extending into said wafer from said first major surface for a distance less than said region of enhanced first type conductivity for controlling blooming, said shallow region of second type conductivity and said region of enhanced first type conductivity for controlling blooming acting in combination to prevent minority carriers from localized sites on the first major surface of the wafer from reaching said regions of second type conductivity extending into said wafer from the second major surface thereof.

Claim 2

A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a first type conductivity, said wafer having first and second major surfaces; forming a capping oxide on at least said second major surface of said wafer; introducing an element through said capping oxide into said second major surface of said wafer so as to form a region of enhanced first type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said wafer; forming an insulating layer on said second major surface of said wafer; providing a plurality of apertures through said insulating layer; forming a plurality of regions of a second type conductivity through said apertures, said second type conductivity regions extending into said wafer from said second surface a distance greater than said region of enhanced first type conductivity; introducing an element into said first major surface of said wafer so as to form a region of enhanced first type conductivity for controlling blooming, said region being spaced from said first major surface; activating said introduced element by heating said wafer at an elevated temperature; and forming a shallow region of a second type conductivity extending into said wafer from said first major surface for a distance less than said region of enhanced first type conductivity for controlling blooming, said shallow region of second type conductivity and said region of enhanced first type conductivity for controlling blooming acting in combination to prevent minority carriers from localized sites on the first major surface of the wafer from reaching said regions of second type conductivity extending into said wafer from the second major surface thereof.

Claim 3

A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a N- type conductivity, said wafer having first and second major surfaces; growing a capping oxide having a thickness of about 300 Å on said second major surface of said wafer; implanting through said capping oxide an element selected from the group consisting of phosphorous and arsenic into said second surface of said wafer so as to form a region of N+ type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said second major surface of said wafer; forming an insulating layer on said second major surface of said wafer; etching a plurality of apertures through said insulating layer; forming a plurality of regions of a P- type conductivity through said apertures, said P- type conductivity regions extending into said wafer from said second major surface a distance greater than said region of N+ type conductivity; implanting arsenic into said first major surface of said wafer so as to form a potential barrier comprising a region of N+ type conductivity for controlling blooming, said region being spaced from said first major surface; annealing said wafer to activate said arsenic atoms implanted into said first major surface; and forming a shallow region of P- type conductivity extending into said wafer from said first major surface for a distance less than said potential barrier, said shallow region of P- type conductivity and said potential barrier acting in combination to prevent holes from localized sites on the first major surface of the wafer from overcoming the potential barrier and reaching the P- type conductivity regions extending into said wafer from the second major surface thereof.

Claim 4

A method of making an imaging device having improved high temperature performance comprising the steps of: preparing a silicon wafer of a N- type conductivity, said wafer having first and second major surfaces; growing a capping oxide having a thickness of about 300 Å on said second major surface of said wafer; implanting through said capping oxide an element selected from the group consisting of phosphorous and arsenic into said second surface of said wafer so as to form a region of N+ type conductivity contiguous with said second major surface of said wafer; annealing said wafer at an elevated temperature and thereafter removing said capping oxide from said second major surface of said wafer; forming an insulating layer on said second major surface of said wafer; etching a plurality of apertures through said insulating layer; forming a plurality of regions of a P- type conductivity through said apertures, said P- type conductivity regions extending into said wafer from said second major surface a distance greater than said region of N+ type conductivity; implanting arsenic into said first major surface of said wafer so as to form a potential barrier comprising a region of N+ type conductivity for controlling blooming, said region being spaced from said first major surface; annealing said wafer to activate said arsenic atoms implanted into said first major surface; and forming a shallow region of P- type conductivity extending into said wafer from said first major surface for a distance less than said potential barrier, said shallow region of P- type conductivity and said potential barrier acting in combination to prevent holes from localized sites on the first major surface of the wafer from overcoming the potential barrier and reaching the P- type conductivity regions extending into said wafer from the second major surface thereof.