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US4546537A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation

Assignee: Fujitsu Ltd
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Filing: 1984-02-10
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Granted: 1985-10-15
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Expires: 2004-02-10
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Abstract

Abstract In a semiconductor device comprising at least one bipolar transistor and a VIP isolating layer which are formed in both an epitaxial layer and a semiconductor substrate, an impurity-introduced region having the same conductivity type as that of the semiconductor substrate is formed so as to surround the V-groove. A buried layer of the bipolar transistor comes into contact with the VIP isolating layer to divide the impurity-introduced region into two parts, one of which is combined with a base region and the other one of which serves as a channel stopper.

Inventors

  • 👤 Yunosuke Kawabe
  • 👤 Yoshinobu Momma

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 06:13
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/40; H10D10/441; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0142; H10W10/041; H10W10/10; H10W10/17; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/117

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 311 words
A method for producing a semiconductor device which comprises at least one bipolar transistor and a VIP isolating layer which are formed in both an epitaxial layer and a semiconductor substrate, with an emitter region of said bipolar transistor coming into contact with said VIP isolating layer, comprising the steps of: forming a buried layer in said semiconductor substrate having a first conductivity type, the buried layer having the opposite conductivity type; forming said epitaxial layer having said opposite conductivity type on said semiconductor substrate; forming a first insulating layer on said epitaxial layer; forming an oxidation masking layer on said first insulating layer; selectively etching said oxidation masking layer and said first insulating layer to form an opening; anisotrophically etching said epitaxial layer and said semiconductor substrate through said opening to form a V-groove, the bottom peak of which enters said semiconductor substrate through said buried layer; introducing impurities having said first conductivity type into exposed portions of said epitaxial layer and said semiconductor substrate in said V-groove; selectively oxidizing said exposed portions in said V-groove to form a second insulating layer; forming a polycrystalline silicon layer on said second insulating layer to fill said V-groove; selectively oxidizing said polycrystalline silicon layer to form a relatively thick insulating layer of silicon dioxide including a bird's beak; removing said oxidation masking layer; forming a base region through a portion of said first insulating layer to have said first conductivity type in said epitaxial layer and in contact with said impurity-introduced region; forming an emitter region having said opposite conductivity type in said base region and in contact with said relatively thick insulating layer; forming an impurity-introduced region for electrical contact, having said opposite conductivity type, in said epitaxial layer outside of said base and emitter regions; and forming electrodes on portions of said base emitter and impurity-introduced regions for electrical contact.
Claim 2
Independent Claim 311 words
A method for producing a semiconductor device which comprises at least one bipolar transistor and a VIP isolating layer which are formed in both an epitaxial layer and a semiconductor substrate, with an emitter region of said bipolar transistor coming into contact with said VIP isolating layer, comprising the steps of: forming a buried layer in said semiconductor substrate having a first conductivity type, the buried layer having the opposite conductivity type; forming said epitaxial layer having said opposite conductivity type on said semiconductor substrate; forming a first insulating layer on said epitaxial layer; forming an oxidation masking layer on said first insulating layer; selectively etching said oxidation masking layer and said first insulating layer to form an opening; anisotrophically etching said epitaxial layer and said semiconductor substrate through said opening to form a V-groove, the bottom peak of which enters said semiconductor substrate through said buried layer; introducing impurities having said first conductivity type into exposed portions of said epitaxial layer and said semiconductor substrate in said V-groove; selectively oxidizing said exposed portions in said V-groove to form a second insulating layer; forming a polycrystalline silicon layer on said second insulating layer to fill said V-groove; selectively oxidizing said polycrystalline silicon layer to form a relatively thick insulating layer of silicon dioxide including a bird's beak; removing said oxidation masking layer; forming a base region through a portion of said first insulating layer to have said first conductivity type in said epitaxial layer and in contact with said impurity-introduced region; forming an emitter region having said opposite conductivity type in said base region and in contact with said relatively thick insulating layer; forming an impurity-introduced region for electrical contact, having said opposite conductivity type, in said epitaxial layer outside of said base and emitter regions; and forming electrodes on portions of said base emitter and impurity-introduced regions for electrical contact.
Claim 3
Dependent Claim 35 words
The method of claim 1, said relatively thick insulating layer extending into said polycrystalline silicon layer to a level below the surface of said epitaxial layer in which said base and emitter regions are formed.
Claim 4
Dependent Claim 19 words
The method of claim 2, wherein poritons of said insulating layer remain in said device over said epitaxial layer.

References Cited (Backward Citations)

US3873383A Cited
US4008107A Cited
US3933540A Cited
US4026736A Cited
US4137109A Cited
US4231057A Cited
US4255207A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-10-14 1989-04-15 1989-10-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-10-14 1993-04-15 1993-10-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-10-14 1997-04-15 1997-10-15 $7700.00 Window Closed / Lapsed

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