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US3873383A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuits with oxidation-junction isolation and channel stop

Assignee: US Philips Corp
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Filing: 1974-01-28
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Granted: 1975-03-25
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Expires: 1994-01-28
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Abstract

Abstract A method of making a semiconductor device in a major surface of a semiconductive body having an inset pattern of insulating material and in which an additional doped zone is provided adjacent to the inset pattern. Prior to the provision of the inset pattern, providing an oxidation and impurity masking layer pattern with apertures at the areas where the inset pattern is to be formed, doping the body through the apertures and thereafter oxidizing the body portions through the apertures, thereby providing oxidation - junction isolation and channel stop.

Inventors

  • 👤 Else Kooi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 01:56
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/676; H10D99/00; H10P; H10P14/00; H10P14/60; H10P14/61; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; H10W74/00; H10W74/40; H10W74/43; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/049; Y10S148/085; Y10S148/117

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 327 words
IN A METHOD OF MAKING A SEMICONDUCTOR DEVICE COMPRISING A SEMICONDUCTOR BODY HAVING AT A MAJOR SURFACE AN INSET PATTERN OF INSULATING MATERIAL FORMING AT LEAST ONE LAYERSHAPED, SURFACE BODY PART ADJOINING THE INSET PATTERN ALONG ITS ENTIRE CIRCUMFERENCE AND THROUGHOUT ITS ENTIRE THICKNESS, AND HAVING AT LEAST ONE CIRCUIT ELEMENT WITH AT LEAST FIRST AND SECOND REGIONS OF A FIRST CONDUCTIVITY TYPE SEPARATED BY A THIRD REGION OF A SECOND CONDUCTIVITY TYPE WITH SAID FIRST AND THIRD REGIONS BEING LOCATED ENTIRELY IN SAID ONE LAYER-SHAPED BODY PART AND SAID SECOND REGION HAVING AT LEAST A PART LOCATED IN SAID ONE LAYER-SHAPED BODY PART AND SAID SECOND REGION PART ADJOINING THE INSET PATTERN ALONG ITS ENTIRE CIRCUMFERENCE, AND HAVING SAID THIRD REGION ADJOINING THE INSET PATTERN ALONG AT LEAST A PART OF ITS CIRCUMFERENCE AND BEING SEPARATED FROM THE MAJOR SURFACE AT LEAST IN PART BY THE FIRST REGION, IN WHICH AN ADDITIONAL DOPED ZONE IS PROVIDED ADJACENT TO THE INSET PATTERN, THE STEPS COMPRISING PRIOR TO PROVISION OF THE INSET PATTERN, PROVIDIG AN OXIDATION AND IMPURITY MASKING LAYER PATTERN ON THE MAJOR SURFACE WITH APERTURES OVER THE SEMICONDUCTOR BODY PORTIONS AT THE AREAS WHERE THE INSET PATTERN IS TO BE FORMED, INTRODUCING SECOND TYPE FORMING IMPURITIES INTO THE BODY THROUGH THE APERTURES WHILE THE OXIDATION AND IMPURITY MASKING LAYER PROTECTS THE BODY PARTS BETWEEN THE APERTURES TO FORM THE SAID ADDITIONAL ZONE, AND THEREAFTER OXIDIZING THE BODY PORTIONS THROUGH THE APERTURES WHILE THE OXIDATION MASKING LAYER PROTECTS THE BDOY PARTS BETWEEN THE APERTURES TO FORM THE INSET PATTERN, THE IMPURITY INTRODUCTION AND OXIDATION STEPS BEING SUCH THAT THE ADDITIONAL DOPED ZONE WHICH FORMS BORDERS THE WHOLE OF THE INSET PATTERN AND CONTAINS A CONCENTRATION OF SECOND TYPE FORMING IMPURITIES WHICH IS SMALLER THAN THE MAXIMUM CONCENTRATION OF FIRST TYPE FORMING IMPURITIES IN THE SECOND REGION BUT STILL SUFFICIENTLY LARGE TO PREVENT IN THE SEMICONDUCTOR ADJACENT THE INSET PATTERN UNDESIRED ELECTRICAL CONNECTIONS BETWEEN SPACED FIRST TYPE REGIONS.
Claim 2
Dependent Claim 327 words
IN A METHOD OF MAKING A SEMICONDUCTOR DEVICE COMPRISING A SEMICONDUCTOR BODY HAVING AT A MAJOR SURFACE AN INSET PATTERN OF INSULATING MATERIAL FORMING AT LEAST ONE LAYERSHAPED, SURFACE BODY PART ADJOINING THE INSET PATTERN ALONG ITS ENTIRE CIRCUMFERENCE AND THROUGHOUT ITS ENTIRE THICKNESS, AND HAVING AT LEAST ONE CIRCUIT ELEMENT WITH AT LEAST FIRST AND SECOND REGIONS OF A FIRST CONDUCTIVITY TYPE SEPARATED BY A THIRD REGION OF A SECOND CONDUCTIVITY TYPE WITH SAID FIRST AND THIRD REGIONS BEING LOCATED ENTIRELY IN SAID ONE LAYER-SHAPED BODY PART AND SAID SECOND REGION HAVING AT LEAST A PART LOCATED IN SAID ONE LAYER-SHAPED BODY PART AND SAID SECOND REGION PART ADJOINING THE INSET PATTERN ALONG ITS ENTIRE CIRCUMFERENCE, AND HAVING SAID THIRD REGION ADJOINING THE INSET PATTERN ALONG AT LEAST A PART OF ITS CIRCUMFERENCE AND BEING SEPARATED FROM THE MAJOR SURFACE AT LEAST IN PART BY THE FIRST REGION, IN WHICH AN ADDITIONAL DOPED ZONE IS PROVIDED ADJACENT TO THE INSET PATTERN, THE STEPS COMPRISING PRIOR TO PROVISION OF THE INSET PATTERN, PROVIDIG AN OXIDATION AND IMPURITY MASKING LAYER PATTERN ON THE MAJOR SURFACE WITH APERTURES OVER THE SEMICONDUCTOR BODY PORTIONS AT THE AREAS WHERE THE INSET PATTERN IS TO BE FORMED, INTRODUCING SECOND TYPE FORMING IMPURITIES INTO THE BODY THROUGH THE APERTURES WHILE THE OXIDATION AND IMPURITY MASKING LAYER PROTECTS THE BODY PARTS BETWEEN THE APERTURES TO FORM THE SAID ADDITIONAL ZONE, AND THEREAFTER OXIDIZING THE BODY PORTIONS THROUGH THE APERTURES WHILE THE OXIDATION MASKING LAYER PROTECTS THE BDOY PARTS BETWEEN THE APERTURES TO FORM THE INSET PATTERN, THE IMPURITY INTRODUCTION AND OXIDATION STEPS BEING SUCH THAT THE ADDITIONAL DOPED ZONE WHICH FORMS BORDERS THE WHOLE OF THE INSET PATTERN AND CONTAINS A CONCENTRATION OF SECOND TYPE FORMING IMPURITIES WHICH IS SMALLER THAN THE MAXIMUM CONCENTRATION OF FIRST TYPE FORMING IMPURITIES IN THE SECOND REGION BUT STILL SUFFICIENTLY LARGE TO PREVENT IN THE SEMICONDUCTOR ADJACENT THE INSET PATTERN UNDESIRED ELECTRICAL CONNECTIONS BETWEEN SPACED FIRST TYPE REGIONS.
Claim 3
Dependent Claim 16 words
A method as claimed in claim 1 wherein the second-type forming impurities are introduced by diffusion.
Claim 4
Dependent Claim 32 words
A method as claimed in claim 2 wherein prior to the diffusion step grooves are formed in the semiconductor bdoy at the areas where the second type impurities are to be diffused.
Claim 5
Dependent Claim 269 words
In a method of making a semiconductor device comprising a semiconductor body having at a major surface an inset pattern of insulating material forming at least one layer-shaped, surface body part adjoining the inset pattern along its entire circumference and throughout its entire thickness, and having at least one circuit element with at least first and second regions of a first conductivity type separated by a third region of a second conductivity type with said first and third regions being located entirely in sAid one layershaped body part and said second region having at least a part located in said one layer-shaped body part and said second region part adjoining the inset pattern along its entire circumference, and having said third region adjoining the inset pattern along at least a part of its circumference and being separated from the major surface at least in part by the first region, in which an additional doped zone is provided adjacent to the inset pattern, the steps comprising providing an oxidation masking layer pattern on the major surface and forming the inset pattern by oxidizing the exposed surface portions, and thereafter diffusing aluminum or gallium as second type forming impurities into the structure, the inset pattern being substantially transparent to the aluminum or gallium whereby the additional doped zone that forms borders the entire inset pattern and contains a concentration of second type forming impurities which is smaller than the maximum concentration of first type forming impurities in the second region but still sufficiently large to prevent in the semiconductor adjacent the inset pattern undesired electrical connections between spaced first type regions.
Claim 6
Dependent Claim 269 words
In a method of making a semiconductor device comprising a semiconductor body having at a major surface an inset pattern of insulating material forming at least one layer-shaped, surface body part adjoining the inset pattern along its entire circumference and throughout its entire thickness, and having at least one circuit element with at least first and second regions of a first conductivity type separated by a third region of a second conductivity type with said first and third regions being located entirely in sAid one layershaped body part and said second region having at least a part located in said one layer-shaped body part and said second region part adjoining the inset pattern along its entire circumference, and having said third region adjoining the inset pattern along at least a part of its circumference and being separated from the major surface at least in part by the first region, in which an additional doped zone is provided adjacent to the inset pattern, the steps comprising providing an oxidation masking layer pattern on the major surface and forming the inset pattern by oxidizing the exposed surface portions, and thereafter diffusing aluminum or gallium as second type forming impurities into the structure, the inset pattern being substantially transparent to the aluminum or gallium whereby the additional doped zone that forms borders the entire inset pattern and contains a concentration of second type forming impurities which is smaller than the maximum concentration of first type forming impurities in the second region but still sufficiently large to prevent in the semiconductor adjacent the inset pattern undesired electrical connections between spaced first type regions.
Claim 7
Dependent Claim 25 words
A method as claimed in claim 4 wherein after the inset pattern is formed and before the diffusion step, the oxidation masking layer is removed.
Claim 8
Dependent Claim 30 words
A method as claimed in claim 5 wherein the aluminum or gallium is diffused after the first region of the first conductivity type has been formed in the semiconductor body.
Claim 9
Dependent Claim 27 words
A method as claimed in claim 5 wherein the additional zone and the third region of the second conductivity type are formed simultaneously in the semiconductor body.

References Cited (Backward Citations)

US3544858A Cited
US3718843A Cited
US3648125A Cited
US3751722A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-03-24 1978-09-23 1979-03-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-03-24 1982-09-23 1983-03-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-03-24 1986-09-23 1987-03-25 $7700.00 Window Closed / Lapsed

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