Patent US4543500A successfully refreshed from Google Patents.
US4543500A
Expired / Lapsed
US
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High performance dynamic sense amplifier voltage boost for row address lines
Assignee: Texas Instruments Inc
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Filing: 1980-10-22
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Granted: 1985-09-24
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Expires: 2000-10-22
Abstract
Abstract A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled drive transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
Inventors
- 👤 Joseph C. McAlexander, III
- 👤 Lionel S. White, Jr.
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/403; G11C11/404; G11C11/409; G11C11/4091; G11C11/4093; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
332 words
A sense amplifier for a semiconductor memory device of the type having an array of rows and columns of memory cells at a face of a semiconductor body with each column split into two column line halves and sense amplifiers connected to pairs of sense nodes at ends of each pair of column line halves, comprising: a pair of cross-coupled driver transistors for each sense amplifier, at least one grounding transistor, and a pair of pull-up transistors for each sense amplifier, each of the transistors having a current path and a control electrode, means connecting the current path of each one of the driver transistors separately between one of the sense nodes and a grounding node and connecting the current path of the grounding transistor between the grounding nodes of a plurality of sense amplifiers and reference potential, the current paths of the pull-up transistors being connected separately between the sense nodes and a supply of a given voltage level, means for precharging the sense nodes to a voltage level prior to an active operating cycle, means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle at a voltage of said voltage level, means for applying a clock voltage to turn on said at least one grounding transistor at a first time subsequent to the said given time in the beginning of an active operating cycle, coupling means separately connecting the control electrodes of the pull-up transistors to the sense nodes, the coupling means being conductive only for a given voltage differential during the active operating cycle, means to boost the voltage on the control electrode of one of the pull-up transistors to higher than said voltage level at a time in the active operating cycle following the first time, said selected row of the memory cells being raised to a voltage higher than said voltage level at a time during said active cycle after said first time.
Claim 2
Dependent Claim
332 words
A sense amplifier for a semiconductor memory device of the type having an array of rows and columns of memory cells at a face of a semiconductor body with each column split into two column line halves and sense amplifiers connected to pairs of sense nodes at ends of each pair of column line halves, comprising: a pair of cross-coupled driver transistors for each sense amplifier, at least one grounding transistor, and a pair of pull-up transistors for each sense amplifier, each of the transistors having a current path and a control electrode, means connecting the current path of each one of the driver transistors separately between one of the sense nodes and a grounding node and connecting the current path of the grounding transistor between the grounding nodes of a plurality of sense amplifiers and reference potential, the current paths of the pull-up transistors being connected separately between the sense nodes and a supply of a given voltage level, means for precharging the sense nodes to a voltage level prior to an active operating cycle, means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle at a voltage of said voltage level, means for applying a clock voltage to turn on said at least one grounding transistor at a first time subsequent to the said given time in the beginning of an active operating cycle, coupling means separately connecting the control electrodes of the pull-up transistors to the sense nodes, the coupling means being conductive only for a given voltage differential during the active operating cycle, means to boost the voltage on the control electrode of one of the pull-up transistors to higher than said voltage level at a time in the active operating cycle following the first time, said selected row of the memory cells being raised to a voltage higher than said voltage level at a time during said active cycle after said first time.
Claim 3
Dependent Claim
23 words
A device according to claim 1 wherein the memory cells are of the dynamic type each having one transistor and one storage capacitor.
Claim 4
Dependent Claim
36 words
A device according to claim 2 wherein all of said transistors are insulated gate field effect transistors, the current path of each of the transistors being a source-to-drain path and the control electrode being a gate.
Claim 5
Dependent Claim
29 words
A device according to claim 1 wherein the means for precharging comprises a pair of precharge transistors having current paths separately connecting a precharge node to said sense nodes.
Claim 6
Dependent Claim
43 words
A device according to claim 4 wherein the precharge node varies in voltage from said voltage level to an intermediate level then to reference potential during an active operating cycle then slowly rises back to said voltage level after an active operating cycle.
Claim 7
Dependent Claim
270 words
A dynamic semiconductor memory device of the type having an array of rows and columns of one-transistor memory cells at a face of a semiconductor body with each column of cells connected to a column line and sense amplifiers connected to sense nodes for column lines, each memory cell having an access transistor and a storage capacitor for storing a zero-level or a one-level, comprising: a pair of cross-coupled driver transistors for each sense amplifier, each of the driver transistors having a current path and a control electrode, means connecting the current path of each one of the driver transistors separately between one of the sense nodes and a grounding node, grounding means for coupling the grounding node to a reference potential, means for precharging the sense nodes to a voltage level prior to an active operating cycle, means for applying an address voltage to a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, said address voltage having a magnitude substantially higher than said voltage level during at least part of such active operating cycle to thereby increase the level of the voltage stored in the storage capacitors of the selected row where a one-level is stored, means for applying a clock voltage to activate said grounding means at a first time subsequent to the said given time in the beginning of an active operating cycle, pull-up means coupled to the column lines to cause a column line for which a one-level was stored to be pulled up to said voltage level after said grounding means is activated.
Claim 8
Dependent Claim
270 words
A dynamic semiconductor memory device of the type having an array of rows and columns of one-transistor memory cells at a face of a semiconductor body with each column of cells connected to a column line and sense amplifiers connected to sense nodes for column lines, each memory cell having an access transistor and a storage capacitor for storing a zero-level or a one-level, comprising: a pair of cross-coupled driver transistors for each sense amplifier, each of the driver transistors having a current path and a control electrode, means connecting the current path of each one of the driver transistors separately between one of the sense nodes and a grounding node, grounding means for coupling the grounding node to a reference potential, means for precharging the sense nodes to a voltage level prior to an active operating cycle, means for applying an address voltage to a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, said address voltage having a magnitude substantially higher than said voltage level during at least part of such active operating cycle to thereby increase the level of the voltage stored in the storage capacitors of the selected row where a one-level is stored, means for applying a clock voltage to activate said grounding means at a first time subsequent to the said given time in the beginning of an active operating cycle, pull-up means coupled to the column lines to cause a column line for which a one-level was stored to be pulled up to said voltage level after said grounding means is activated.
Claim 9
Dependent Claim
231 words
A dynamic semiconductor memory device comprising: an array of rows and columns of one-transistor memory cells at a face of a semiconductor body with each column of cells connected to a column line, a plurality of sense amplifiers connected to sense nodes on the column lines, each memory cell having an access transistor and a storage capacitor for storing data as a one-level or a zero-level, each sense amplifier having a pair of cross-coupled driver transistors, each of the driver transistors having a current path and a control electrode, with means connecting the current path of each one of the driver transistors separately between one of the sense nodes and grounding means, means for precharging the column lines to a voltage level prior to an active operating cycle, pull-up means coupled to the column lines to pull a column line for which a one-level is stored up to said voltage level after the beginning of an active operating cycle, and means for applying an address voltage to a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, said address voltage having a magnitude substantially higher than said voltage level during at least part of such active operating cycle to thereby increase the level of the voltage stored in the storage capacitors of the selected row where a one-level is stored.
Claim 10
Dependent Claim
231 words
A dynamic semiconductor memory device comprising: an array of rows and columns of one-transistor memory cells at a face of a semiconductor body with each column of cells connected to a column line, a plurality of sense amplifiers connected to sense nodes on the column lines, each memory cell having an access transistor and a storage capacitor for storing data as a one-level or a zero-level, each sense amplifier having a pair of cross-coupled driver transistors, each of the driver transistors having a current path and a control electrode, with means connecting the current path of each one of the driver transistors separately between one of the sense nodes and grounding means, means for precharging the column lines to a voltage level prior to an active operating cycle, pull-up means coupled to the column lines to pull a column line for which a one-level is stored up to said voltage level after the beginning of an active operating cycle, and means for applying an address voltage to a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, said address voltage having a magnitude substantially higher than said voltage level during at least part of such active operating cycle to thereby increase the level of the voltage stored in the storage capacitors of the selected row where a one-level is stored.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-23 | 1989-03-25 | 1989-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-23 | 1993-03-25 | 1993-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-23 | 1997-03-25 | 1997-09-24 | $7700.00 | Window Closed / Lapsed |