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US4520309A
Expired / Lapsed
US
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System for testing the malfunctioning or correct operation of a circuit with logic components
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1982-03-05
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Granted: 1985-05-28
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Expires: 2002-03-05
Abstract
Abstract The invention relates to a system for testing the malfunctioning or correct operation of a circuit with n logic components. These components respectively present a simulation input receiving a malfunctioning or correct operation simulation signal. The system is characterized in that it comprises test means for placing each component respectively in a state of malfunctioning or of correct operation and vice versa, for one or more combinations of the components of the circuit, the test means present a characteristic output which furnishes a signal of which the logic level depends on the state of malfunctioning or of correct operation and vice versa, of each of the components of the circuit. Finally, the system comprises stop means for stopping the test means when the tests to be carried out are finished. The invention is more particularly applied to tests of electronic circuits and, by analogy, to tests of hydraulic circuits.
Inventors
- 👤 Andre Laviron
- 👤 Claude Berard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:21
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
353 words
A system for testing the operation of a circuit having n components and an output, said system comprising: storage means having a first input connected to the output of said circuit, a second input and an output; a set of at least n flip flops, each having an output and at least one input, each of said ouputs being connected as an input to a corresponding one of said n components; a logic assembly for selection and control of the flip-flops having at least n segments each of said segments corresponding to one of said n flip flops, each of said segments having an output connected to the input of the corresponding flip flop, a first input and two control inputs; a shift register containing at least n stages connected in series, each of said stages corresponding to one of said flip flops and one of said segments and having an output connected to the first input of the corresponding segment, said shift register having a return to zero input, a signal input and a shift input; a logic synchronization means having first and second outputs connected to said two control inputs of each segment of said logic assembly, third, fourth and fifth outputs connected to said return to zero input, said signal input and said shift input of first stage of said shift register, a sixth output connected to the second input of said storage means and an input connected to the output of said storage means; wherein a signal to said input to said component causes said component to malfunction and wherein said synchronization means produces a logic pattern within said shift register through said signal input, causing selected ones of said segments and said flip flops to receive an input signal, and selected ones of said components to malfunction, said synchronization means changing the output of one segment at a time through said two control inputs so that the state of malfunctioning of the corresponding component is changed, the storage means producing a signal on said output to indicate a change in the output of the circuit in response thereto.
Claim 2
Independent Claim
353 words
A system for testing the operation of a circuit having n components and an output, said system comprising: storage means having a first input connected to the output of said circuit, a second input and an output; a set of at least n flip flops, each having an output and at least one input, each of said ouputs being connected as an input to a corresponding one of said n components; a logic assembly for selection and control of the flip-flops having at least n segments each of said segments corresponding to one of said n flip flops, each of said segments having an output connected to the input of the corresponding flip flop, a first input and two control inputs; a shift register containing at least n stages connected in series, each of said stages corresponding to one of said flip flops and one of said segments and having an output connected to the first input of the corresponding segment, said shift register having a return to zero input, a signal input and a shift input; a logic synchronization means having first and second outputs connected to said two control inputs of each segment of said logic assembly, third, fourth and fifth outputs connected to said return to zero input, said signal input and said shift input of first stage of said shift register, a sixth output connected to the second input of said storage means and an input connected to the output of said storage means; wherein a signal to said input to said component causes said component to malfunction and wherein said synchronization means produces a logic pattern within said shift register through said signal input, causing selected ones of said segments and said flip flops to receive an input signal, and selected ones of said components to malfunction, said synchronization means changing the output of one segment at a time through said two control inputs so that the state of malfunctioning of the corresponding component is changed, the storage means producing a signal on said output to indicate a change in the output of the circuit in response thereto.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |