Bidirectional data byte aligner

Claim 2

In combination: system bus means for delivering digital bytes of information to a memory means and receiving digital bytes of information from said memory means; transceiver means for transferring at least one of a plurality of said digital bytes between said memory means and said system bus means; first byte bus means for transferring at least one of said bytes between said system bus and a first port of said transceiver means; second byte bus means for transferring at least one of said bytes between a second port of said transceiver means and said memory means; means for controlling writing and reading memory accesses starting at any byte location within said memory means; and means for controlling said transceiver means when transferring at least one of said bytes between said memory means and said system bus.

Claim 3

The combination as recited in claim 1 wherein: said memory means includes at least one even-address memory segment and at least one odd-address memory segment, said memory segments capable of being accessed simultaneously to provide memory access for a plurality of sequential bytes.

Claim 4

The combination as recited in claim 1 wherein: said transceiver means comprises a plurality of bidirectional transceiver arrays.

Claim 5

The combination as recited in claim 3 wherein: each of said bidirectional transceiver arrays further comprises a plurality of multiple bit bidirectional bus transceivers.

Claim 6

The combination as recited in claim 1 wherein: said memory access controlling means further comprises means for writing and reading a plurality of bytes extending across said memory segment boundaries.

Claim 7

The combination as recited in claim 1 wherein: said memory controlling means and said transceiver controlling means comprise a plurality of programmable logic arrays.

Claim 8

In combination: system bus means for delivering digital bytes of information to a memory means and receiving digital bytes of information from said memory means; transceiver means for transferring at least one of a plurality of said digital bytes between said memory means and said system bus means; first byte bus means for transferring at least one of said bytes between said system bus and a first port of said transceiver means; second byte bus means for transferring at least one of said bytes between a second port of said transceiver means and said memory means; means for controlling writing and reading memory accesses starting at any byte location within said memory means; means for controlling said transceiver means when transferring at least one of said bytes between said memory means and said system bus; means for performing right-justified zero-extension when transferring at least one of said bytes during a read memory cycle; and means for performing right-justified sign-extension when transferring at least one of said bytes during a read memory cycle.

Claim 9

In combination: system bus means for delivering digital bytes of information to a memory means and receiving digital bytes of information from said memory means; transceiver means for transferring at least one of a plurality of said digital bytes between said memory means and said system bus means; first byte bus means for transferring at least one of said bytes between said system bus and a first port of said transceiver means; second byte bus means for transferring at least one of said bytes between a second port of said transceiver means and said memory means; means for controlling writing and reading memory accesses starting at any byte location within said memory means; means for controlling said transceiver means when transferring at least one of said bytes between said memory means and said system bus; means for performing right-justified zero-extension when transferring at least one of said bytes during a read memory cycle; and means for performing right-justified sign-extension when transferring at least one of said bytes during a read memory cycle.

Claim 10

The combination as recited in claim 7 wherein: said memory means includes at least one even-address memory segment and at least one odd-address memory segment, said memory segments capable of being accessed simultaneously to provide memory access for a plurality of sequential bytes.

Claim 11

The combination as recited in claim 7 wherein: said transceiver means comprises a plurality of bidirectional transceiver arrays.

Claim 12

The combination as recited in claim 9 wherein: each of said bidirectional transceiver arrays further comprises a plurality of multiple bit bidirectional bus transceivers.

Claim 13

The combination as recited in claim 7 wherein: said memory access controlling means further comprises means for writing and reading a plurality of bytes extending across said memory segment boundaries.

Claim 14

The combination as recited in claim 7 wherein: said memory controlling means and said transceiver controlling means comprise a plurality of programmable logic arrays.

Claim 15

The combination as recited in claim 8 wherein: each of said memory segments comprises identical sets of a plurality of programmable logic arrays.

Claim 16

The combination as recited in claim 7 wherein: said sign-extension means comprises means for examining a most significant bit of a most significant byte for said sign extension determination.

Claim 17

In combination: memory means for storing a plurality of digital bytes of information, said memory means comprising at least one even-address memory segment and at least one odd-address memory segment; byte aligner means for accessing a byte of information at any one of a plurality of byte locations in said memory means within one memory cycle and for accessing a plurality of sequential bytes starting at any byte location in said memory means within one memory cycle; and said byte aligner means comprising a system bus means for delivering said digital bytes to said memory means and receiving said digital bytes from said memory means.

Claim 18

In combination: memory means for storing a plurality of digital bytes of information, said memory means comprising at least one even-address memory segment and at least one odd-address memory segment; byte aligner means for accessing a byte of information at any one of a plurality of byte locations in said memory means within one memory cycle and for accessing a plurality of sequential bytes starting at any byte location in said memory means within one memory cycle; and said byte aligner means comprising a system bus means for delivering said digital bytes to said memory means and receiving said digital bytes from said memory means.

Claim 19

The combination as recited in claim 15 wherein: said even-address memory segment and said odd-address memory segment comprise means for being accessed simultaneously in one memory cycle time to provide memory access for a plurality of sequential bytes.

Claim 20

The combination as recited in claim 15 wherein: each of said memory segments comprises byte aligner means interconnected by said system bus.

Claim 21

The combination as recited in claim 15 wherein: said memory means accesses comprise read memory cycles and write memory cycles.

Claim 22

The combination as recited in claim 15 wherein: said byte aligner means comprises a plurality of bidirectional transceiver arrays.

Claim 23

The combination as recited in claim 19 wherein: each of said bidirectional transceiver arrays further comprise a plurality of multiple bit bidirectional bus transceivers.

Claim 24

The combination as recited in claim 15 wherein: said byte aligner means further comprises a plurality of programmed logic arrays.

Claim 25

The combination as recited in claim 21 wherein: said programmed logic arrays comprise means for generating control signals for said memory means and a bidirectional transceiver array.

Claim 26

The combination as recited in claim 15 wherein: said byte aligner means further comprises means for performing right-justified zero-extension when transferring at least one of said bytes to said system bus from said memory means during a read memory cycle, and means for performing right-justified sign-extension when transferring at least one of said bytes to said system bus from said memory means during a read memory cycle.

Claim 27

In combination: memory means for storing a plurality of digital bytes of information, said memory means comprising at least one even-address memory segment and at least one odd-address memory segment; system bus means for delivering digital bytes of information to said memory means and receiving digital bytes of information from said memory means; first byte bus means for transferring at least one of said bytes between said system bus and a first port of said transceiver means; second byte bus means for transferring at least one of said bytes between a second port of said transceiver means and said memory means; means for controlling writing and reading memory accesses starting at any byte location within said memory means; and means for controlling said transceiver means when transferring at least one of said bytes between said memory means and said system bus.

Claim 28

In combination: memory means for storing a plurality of digital bytes of information, said memory means comprising at least one even-address memory segment and at least one odd-address memory segment; system bus means for delivering digital bytes of information to said memory means and receiving digital bytes of information from said memory means; first byte bus means for transferring at least one of said bytes between said system bus and a first port of said transceiver means; second byte bus means for transferring at least one of said bytes between a second port of said transceiver means and said memory means; means for controlling writing and reading memory accesses starting at any byte location within said memory means; and means for controlling said transceiver means when transferring at least one of said bytes between said memory means and said system bus.

Claim 29

The combination as recited in claim 24 wherein: said even-address memory segment and said odd-address memory segment comprise means for being accessed simultaneously to provide memory access for a plurality of sequential bytes.

Claim 30

The combination as recited in claim 24 wherein: said transceiver means comprises a plurality of bidirectional transceiver arrays.

Claim 31

The combination as recited in claim 26 wherein: each of said bidirectional transceiver arrays further comprises a plurality of multiple bit bidirectional bus transceivers.

Claim 32

The combination as recited in claim 24 wherein: said memory access controlling means further comprises means for writing and reading a plurality of bytes extending across said memory segment boundaries.

Claim 33

The combination as recited in claim 24 wherein: said memory controlling means and said transceiver controlling means comprise a plurality of programmable logic arrays.

Claim 34

In combination: memory means for storing a plurality of digital bytes of information, said memory means comprising at least one even-address memory segment and at least one odd-address memory segment; system bus means for delivering digital bytes of information to said memory means and receiving digital bytes of information from said memory means; transceiver means for transferring at least one of a plurality of said digital bytes between said memory means and said system bus means; first byte bus means for transferring at least one of said bytes between said system bus and a first port of said transceiver means; second byte bus means for transferring at least one of said bytes between a second port of said transceiver means and said memory means; means for controlling writing and reading memory accesses starting at any byte location within said memory means; means for controlling said transceiver means when transferring at least one of said bytes between said memory means and said system bus; means for performing right-justified zero-extension when transferring at least one of said bytes during a read memory cycle; and means for performing right-justified sign-extension when transferring at least one of said bytes during a read memory cycle.

Claim 35

In combination: memory means for storing a plurality of digital bytes of information, said memory means comprising at least one even-address memory segment and at least one odd-address memory segment; system bus means for delivering digital bytes of information to said memory means and receiving digital bytes of information from said memory means; transceiver means for transferring at least one of a plurality of said digital bytes between said memory means and said system bus means; first byte bus means for transferring at least one of said bytes between said system bus and a first port of said transceiver means; second byte bus means for transferring at least one of said bytes between a second port of said transceiver means and said memory means; means for controlling writing and reading memory accesses starting at any byte location within said memory means; means for controlling said transceiver means when transferring at least one of said bytes between said memory means and said system bus; means for performing right-justified zero-extension when transferring at least one of said bytes during a read memory cycle; and means for performing right-justified sign-extension when transferring at least one of said bytes during a read memory cycle.

Claim 36

The combination as recited in claim 30 wherein: said even-address memory segment and said odd-address memory segment comprise means for being accessed simultaneously to provide memory access for a plurality of sequential bytes.

Claim 37

The combination as recited in claim 30 wherein: said transceiver means comprises a plurality of bidirectional transceiver arrays.

Claim 38

The combination as recited in claim 32 wherein: each of said bidirectional transceiver arrays further comprises a plurality of multiple bit bidirectional bus transceivers.

Claim 39

The combination as recited in claim 30 wherein: said memory access controlling means further comprises means for writing and reading a plurality of bytes extending across said memory segment boundaries.

Claim 40

The combination as recited in claim 30 wherein: said memory controlling means and said transceiver controlling means comprise a plurality of programmable logic arrays.

Claim 41

The combination as recited in claims 31 wherein: each of said memory segments comprises identical sets of a plurality of programmable logic arrays.

Claim 42

The combination as recited in claim 30 wherein: said sign-extension means comprises means for examining a most significant bit of a most significant byte for said sign extension determination.

Claim 43

In combination: a bidirectional transceiver array comprising a plurality of multiple bit bidirectional transceivers, each transceiver having the capability of transferring at least one byte of digital information; a first bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a system bus to a first port of a first grouping of said transceivers in parallel with each other; said system bus connected to a plurality of said first bus for delivering and receiving digital information comprising a plurality of bytes to and from an even-address memory segment and an odd-address memory segment; a second bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a memory array of said memory segments to a second port of a second grouping of said transceivers in parallel with each other; memory control logic, responsive to memory addressing signals, connected to said memory array for controlling writing and reading accesses on byte boundaries within each of said memory segments and across said memory segment boundaries; and transceiver control logic, responsive to memory addressing signals, connected to said transceiver array for controlling the transfer of at least one byte of said plurality of bytes of information between said memory array and said system bus.

Claim 44

In combination: a bidirectional transceiver array comprising a plurality of multiple bit bidirectional transceivers, each transceiver having the capability of transferring at least one byte of digital information; a first bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a system bus to a first port of a first grouping of said transceivers in parallel with each other; said system bus connected to a plurality of said first bus for delivering and receiving digital information comprising a plurality of bytes to and from an even-address memory segment and an odd-address memory segment; a second bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a memory array of said memory segments to a second port of a second grouping of said transceivers in parallel with each other; memory control logic, responsive to memory addressing signals, connected to said memory array for controlling writing and reading accesses on byte boundaries within each of said memory segments and across said memory segment boundaries; and transceiver control logic, responsive to memory addressing signals, connected to said transceiver array for controlling the transfer of at least one byte of said plurality of bytes of information between said memory array and said system bus.

Claim 45

The combination as recited in claim 38 wherein: said even-address memory segment and said odd-address memory segment comprise means for being accessed simultaneous to provide memory access for a plurality of sequential bytes.

Claim 46

The combination as recited in claim 38 wherein: said first grouping of said transceivers provide for a byte of said system bus to be transferred to and from any byte position in said memory array.

Claim 47

The combination as recited in claim 38 wherein: said second grouping of said transceivers provide for a byte of said memory array to be transferred to and from any byte position of said system bus.

Claim 48

The combination as recited in claim 38 wherein: said memory control logic and said transceiver control logic comprise a plurality of programmable logic arrays.

Claim 49

In combination: a bidirectional transceiver array comprising a plurality of multiple bit bidirectional transceivers, each transceiver having the capability of transferring at least one byte of digital information; a first bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a system bus to a first port of a first grouping of said transceivers in parallel with each other; said system bus connected to a plurality of said first bus for delivering and receiving digital information comprising a plurality of bytes to and from an even-address memory segment and an odd-address memory segment; a second bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a memory array of said memory segments to a second port of a second grouping of said transceivers in parallel with each other; memory control logic, responsive to memory addressing signals, connected to said memory array for controlling writing and reading accesses on byte boundaries within each of said memory segments and across said memory segment boundaries; transceiver control logic, responsive to memory addressing signals, connected to said transceiver array for controlling the transfer of at least one byte of said plurality of bytes of information between said memory array and said system bus; means coupled to said memory control logic for performing right-justified zero-extension when transferring at least one of said bytes during a read memory cycle; and means coupled to said memory control logic for performing right-justified sign-extension when transferring at least one of said bytes during a read memory cycle.

Claim 50

In combination: a bidirectional transceiver array comprising a plurality of multiple bit bidirectional transceivers, each transceiver having the capability of transferring at least one byte of digital information; a first bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a system bus to a first port of a first grouping of said transceivers in parallel with each other; said system bus connected to a plurality of said first bus for delivering and receiving digital information comprising a plurality of bytes to and from an even-address memory segment and an odd-address memory segment; a second bus comprising a plurality of bytes, each of said bus bytes connecting a byte of a memory array of said memory segments to a second port of a second grouping of said transceivers in parallel with each other; memory control logic, responsive to memory addressing signals, connected to said memory array for controlling writing and reading accesses on byte boundaries within each of said memory segments and across said memory segment boundaries; transceiver control logic, responsive to memory addressing signals, connected to said transceiver array for controlling the transfer of at least one byte of said plurality of bytes of information between said memory array and said system bus; means coupled to said memory control logic for performing right-justified zero-extension when transferring at least one of said bytes during a read memory cycle; and means coupled to said memory control logic for performing right-justified sign-extension when transferring at least one of said bytes during a read memory cycle.

Claim 51

The combination as recited in claim 43 wherein: said even-address memory segment and said odd-address memory segment comprise means for being accessed simultaneous to provide memory access for a plurality of sequential bytes.

Claim 52

The combination as recited in claim 43 wherein: said first grouping of said transceivers provide for a byte of said system bus to be transferred to and from any byte in said memory array.

Claim 53

The combination as recited in claim 43 wherein: said second grouping of said transceivers provide for a byte of said memory array to be transferred to and from any byte position of said system bus.

Claim 54

The combination as recited in claim 43 wherein: said memory control logic and said transceiver control logic comprise a plurality of programmable logic arrays.

Claim 55

The combination as recited in claim 43 wherein: said sign-extension means comprises means for examining a most significant bit of a most significant byte for said sign extension determination.

Claim 58

The method as recited in claim 49 wherein: said memory means comprises at least one even-address memory array and at least one odd-address memory array, said memory arrays capable of being accessed simultaneously to provide memory access for a plurality of sequential bytes.

Claim 59

The method as recited in claim 50 wherein: said step of controlling the writing and reading cycles for said digital bytes comprises means for starting at any byte location within said memory means and extending across said memory array boundaries.

Claim 60

The method as recited in claim 49 wherein: said bidirectional transceiver means comprises a plurality of bidirectional transceiver arrays, each of said arrays further comprises a plurality of multiple bit bidirectional bus transceivers.

Claim 63

The method as recited in claim 53 wherein: said memory means comprises at least one even-address memory array and at least one odd-address memory array, said memory arrays capable of being accessed simultaneously to provide memory access for a plurality of sequential bytes.

Claim 64

The method as recited in claim 54 wherein: said step of controlling the writing and reading cycles for said digital bytes comprises means for starting at any byte location within said memory means and extending across said memory array boundaries.

Claim 65

The method as recited in claim 53 wherein: said bidirectional transceiver means comprises a plurality of bidirectional transceiver arrays, each of said arrays further comprises a plurality of multiple bit bidirectional bus transceivers.

Claim 66

The method as recited in claim 53 wherein: said steps of performing right-justified sign-extension comprises means for examining a most significant bit of a most significant byte for sign extension determination.