Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
90 words
A memory system comprising a plurality of rows of memory chips, each row containing a plurality of word locations running along the row, characterized in that successive addresses (Fig. 6b) are located in successive rows (Fig. 4c) in cyclic sequence, and the addressing circuitry (207, Fig. 4b) includes row select circuitry (207-2) responsive to the low order end of a desired address to select the row containing that address and the next row in cyclic sequence, to enable also the selection of the next address adjacent to the desired address.
Claim 2
Dependent Claim
90 words
A memory system comprising a plurality of rows of memory chips, each row containing a plurality of word locations running along the row, characterized in that successive addresses (Fig. 6b) are located in successive rows (Fig. 4c) in cyclic sequence, and the addressing circuitry (207, Fig. 4b) includes row select circuitry (207-2) responsive to the low order end of a desired address to select the row containing that address and the next row in cyclic sequence, to enable also the selection of the next address adjacent to the desired address.
Claim 3
Dependent Claim
59 words
A memory system according to Claim 1, characterized in that the higher order part of the desired address is fed to the row containing the desired address, and is also fed to the next row in sequence via an increment-by-1 circuit (207-54) if that row is a predetermined row and direct if that row is not the predetermined row.
Claim 4
Dependent Claim
43 words
A memory system according to Claim 1 or to Claim 2 where the size of the increment-by-1 circuit (207-54) is limited, characterized by boundary detection circuitry (207-15) which detects when the address selected by the-addressing circuitry is not adjacent to the desired address.
Claim 5
Dependent Claim
60 words
A memory system according to any previous claim, characterized in that the row select circuitry (207-2) comprises decoding circuitry (207-20, 207-40) having a plurality of outputs corresponding to the number of rows, and a set of gates (207-24 to 30, 207-44 to 50), one for each row, each fed with 2 adjacent outputs of the decoding circuitry in cyclic sequence.
Claim 6
Dependent Claim
75 words
A memory system according to any previous claim, characterized by timing circuitry (Fig. 4a) which generates a sequence of timing signals, and in that the addressing circuitry includes a pair of tristate registers (207-40, 207-42) which are multiplexed onto a common bus to the memory chips and which have their contents sequentially fed over that bus, under the control of the timing circuitry, to the memory chips to store chip-row and chip-column addresses sequentially therein.
Claim 7
Dependent Claim
54 words
A memory system according to any previous claim characterized by a plurality of data registers (206-8, 206-10) each row being coupled to one of the data registers, and a multiword bus (BSDTOO-31) to which the data registers are coupled, whereby a plurality of words can be transferred by the system in a single cycle.
Claim 8
Dependent Claim
38 words
A memory system according to Claim 6, characterized by multiplexer circuitry (206-4, 206-16, 206-18) coupling the data registers are the bus, whereby the word with the desired address appears in the lowest order word position on the bus.