Input buffer circuit for receiving multiple level input voltages

Claim 2

An input buffer circuit for receiving multiple level input voltages comprising: a first inverter having an input for receiving an input voltage which has an amplitude which varies by one of a plurality of levels, and an output; a second inverter coupled to the first inverter and having an input for receiving the input voltage, and an output; voltage level shifting means having a first input coupled to the output of the first inverter, a second input connected to the output of the second inverter, and first and second outputs for buffering and shifting the input voltage a predetermined amount; a first capacitor having a first electrode coupled to the first output of the voltage level shifting means, and a second electrode; a second capacitor having a first electrode coupled to the second output of the voltage level shifting means, and a second electrode; and latching means coupled to the second electrodes of the first and second capacitors for latching the voltage level due to the charge on the first and second capacitors and providing an output.

Claim 3

The input buffer circuit of claim 1 wherein said voltage level shifting means further comprise: first voltage level shifting means having an input connected to the output of the first inverter, and an output for shifting the level of the input voltage a first predetermined amount; and second voltage level shifting means having an input connected to the output of the second inverter, and an output for shifting the level of the input voltage a second predetermined amount.

Claim 4

The input buffer circuit of claim 1 wherein said first inverter comprises: a bipolar transistor having a first current electrode connected to both a control electrode thereof and a terminal for receiving a first supply voltage, and a second current electrode; a second transistor of a first conductivity type having a first current electrode connected to the second current electrode of the bipolar transistor, a control electrode connected to the input voltage, and a second current electrode connected to the input of the first voltage level shifting means; and a third transistor of a second conductivity type having a first current electrode connected to the the second current electrode of the second transistor, a control electrode connected to the input voltage, and a second current electrode connected to both the second inverter and a terminal for receiving a second supply voltage.

Claim 5

The input buffer circuit of claim 3 wherein said second inverter comprises: a fourth transistor of the first conductivity type having a first current electrode connected to the terminal for receiving the second supply voltage, a control electrode connected to the input voltage, and a second current electrode conntected to the input of the second voltage level shifting means; and a fifth transistor of the second conductivity type having a first current electode connected to the second current electrode of the fourth transistor, a control electrode connected to the control electrode, and a second current electrode connected to a terminal for receiving a third supply voltage.

Claim 6

An input buffer circuit for receiving multiple level input voltages comprising: a first inverter having an input for receiving an input voltage, an output, and a first predetermined switch point; a second inverter connected to the first inverter and having an input for receiving the input voltage, and output, and a second predetermined switch point; first voltage level shifting means having an input coupled to the output of the first inverter, and an output for shifting the level of the input voltage a predetermined amount; a second voltage level shifting means having an input coupled to the output of the second inverter, and an output for shifting the level of the input voltage a predetermined amount; and a third inverter having an input coupled to the output of the first voltage level shifting means, and an output; a fourth inverter having an input coupled to the output of the second voltage level shifting means, and an output; a first capacitor having a first electrode coupled to the third inverter, and a second electrode; a second capacitor having a first electrode coupled to the fourth inverter, and a second electrode; a fifth inverter having an input coupled to the second electrodes of the first and second capacitors, and an output for providing a buffered output signal of predetermined voltage level in response to the input voltage; and a sixth inverter having an input coupled to the output of the fifth inverter, and an output coupled to the input of the first inverter, said sixth inverter thereby raising the voltage level at which the fifth inverter switches.

Claim 7

An input buffer circuit for receiving multiple level input voltages comprising: a first inverter having an input for receiving an input voltage, an output, and a first predetermined switch point; a second inverter connected to the first inverter and having an input for receiving the input voltage, and output, and a second predetermined switch point; first voltage level shifting means having an input coupled to the output of the first inverter, and an output for shifting the level of the input voltage a predetermined amount; a second voltage level shifting means having an input coupled to the output of the second inverter, and an output for shifting the level of the input voltage a predetermined amount; and a third inverter having an input coupled to the output of the first voltage level shifting means, and an output; a fourth inverter having an input coupled to the output of the second voltage level shifting means, and an output; a first capacitor having a first electrode coupled to the third inverter, and a second electrode; a second capacitor having a first electrode coupled to the fourth inverter, and a second electrode; a fifth inverter having an input coupled to the second electrodes of the first and second capacitors, and an output for providing a buffered output signal of predetermined voltage level in response to the input voltage; and a sixth inverter having an input coupled to the output of the fifth inverter, and an output coupled to the input of the first inverter, said sixth inverter thereby raising the voltage level at which the fifth inverter switches.

Claim 8

The input buffer circuit of claim 5 wherein said first inverter comprises: a bipolar transistor having a first current electrode coupled to both a control electrode thereof and a terminal for receiving a first supply voltage, and a second current electrode; a second transistor of a first conductivity type having a first current electrode coupled to the second current electrode of the bipolar transistor, a control electrode coupled to the input voltage, and a second current electrode coupled to the input of the first voltage level shifting means; and a third transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the input voltage, and a second current electrode coupled to both the second inverter and a terminal for receiving a second supply voltage.

Claim 9

The input buffer circuit of claim 6 wherein said second inverter comprises: a fourth transistor of the first conductivity type having a first current electrode coupled to the terminal for receiving the second supply voltage, a control electrode coupled to the input voltage, and a second current electrode coupled to the input of the second voltage level shifting means; and a fifth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode coupled to the control electrode, and a second current electrode coupled to a terminal for receiving a third supply voltage.

Claim 10

An input buffer circuit for receiving multiple level input voltages comprising: a first inverter having an input for receiving an input voltage, an output, and a first predetermined switch point; a second inverter coupled to the first inverter and having an input for receiving the input voltage, an output, and a second predetermined switch point; voltage level shifting means having a first input coupled to the output of the first inverter, a second input coupled to the output of the second inverter, a first output for shifting the level of the input voltage a first predetermined amount, and a second output for shifting the level of the input voltage a second predetermined amount; coupling means having first and second inputs coupled to the first and second outputs of the voltage level shifting means, respectively, first and second outputs coupled to an output terminal for providing an output signal having a predetermined voltage level, and first and second control terminals; and control means coupled to the coupling means, for actuating the coupling means in response to the input voltage.

Claim 11

An input buffer circuit for receiving multiple level input voltages comprising: a first inverter having an input for receiving an input voltage, an output, and a first predetermined switch point; a second inverter coupled to the first inverter and having an input for receiving the input voltage, an output, and a second predetermined switch point; voltage level shifting means having a first input coupled to the output of the first inverter, a second input coupled to the output of the second inverter, a first output for shifting the level of the input voltage a first predetermined amount, and a second output for shifting the level of the input voltage a second predetermined amount; coupling means having first and second inputs coupled to the first and second outputs of the voltage level shifting means, respectively, first and second outputs coupled to an output terminal for providing an output signal having a predetermined voltage level, and first and second control terminals; and control means coupled to the coupling means, for actuating the coupling means in response to the input voltage.

Claim 12

The input buffer circuit of claim 8 wherein said voltage level shifting means further comprise: first voltage level shifting means having an input coupled to the output of the first inverter, and an output for shifting the level of the input voltage a first predetermined amount; and second voltage level shifting means having an input coupled to the output of the second inverter, and an output for shifting the level of the input voltage a second predetermined amount.

Claim 13

The input buffer circuit of claim 9 wherein said first inverter comprises: a bipolar transistor having a first current electrode coupled to both a control electrode thereof and to a terminal for receiving a first supply voltage, and a second current electrode; a second transistor of a first conductivity type having a first current electrode coupled to the second current electrode of the bipolar transistor, a control electrode coupled to the input voltage, and a second current electrode coupled to the input of the first voltage level shifting means; and a third transistor of a second conductivity type having a first current electrode coupled to the the second current electrode of the second transistor, a control electrode coupled to the input voltage, and a second current electrode coupled to both the second inverter and a terminal for receiving a second supply voltage.

Claim 14

The input buffer circuit of claim 9 wherein said second inverter comprises: a fourth transistor of the first conductivity type having a first current electrode coupled to the terminal for receiving the second supply having a first current electrode coupled to the second current electrode of the bipolar transistor, a control electrode coupled to the input voltage, and a second current electrode coupled to the input of the first voltage level shifting means; and a fifth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode coupled to the control electrode, and a second current electrode coupled to a terminal for receiving a third supply voltage.