Speed up circuit

Claim 2

The combination comprising: first and second power terminals for the application thereto of first and second operating potentials, respectively; first and second input terminals for the application thereto of complementary input signals; first and second outputs at which are produced output signals in response to said input signals; first and second switching transistors, each having a conduction path and a control electrode; means connecting the conduction paths of said first and second transistors between said first and second outputs, respectively, and said first power terminal; means connecting the control electrodes of said first and second transistors to said first and second input terminals, respectively; third, fourth, fifth and sixth transistors each having a conduction path and a control electrode; said third and fourth transistors, when turned-on, having a much higher impedance than the ON-impedance of said first, second, fifth and sixth transistors; means connecting the conduction paths of said third and fifth transistors in parallel between said first output and said second power terminal; means connecting the conduction paths of said fourth and sixth transistors in parallel between said second output and said second power terminal; means coupling the control electrode of said third transistor to said second output and the control electrode of said fourth transistor to said first output; and means responsive to the signal at said first and second outputs coupled to the control electrodes of said fifth and sixth transistors for momentarily turning-on the fifth transistor and maintaining the sixth transistor turned-off when said second transistor is initially turned-on; and for momentarily turning-on the sixth transistor and maintaining said fifth transistor turned off when said first transistor is initially turned-on.

Claim 3

The combination as claimed in claim 1 wherein said transistors are insulated-gate field-effect transistors (IGFETs).

Claim 4

The combination as claimed in claim 2 when said first and second transistors are of one conductivity type and said third, fourth, fifth and sixth transistors are of opposite conductivity type.

Claim 5

The combination as claimed in claim 1 wherein said means responsive to the signal at said first and second outputs includes means responsive to a signal at one of said first and second outputs making a transition from a voltage level approximately equal to that at said second power terminal to a voltage level approximately equal to that at said first power terminal for turning-on that one of said fifth and sixth transistor connected to the other one of said first and second outputs and rapidly charging said other one of said first and second outputs to, or close to, the voltage level at said second power terminal; and wherein said means responsive to the signal at said first and second outputs includes means responsive to the signal at said other one of said first and second outputs being charged to said second power terminal and said one of said first and second outputs being charged to the voltage at said first power terminal for turning-off said one of said fifth and sixth transistors.

Claim 6

The combination as claimed in claim 1 wherein said means responsive to the signal at said first and second outputs includes: a bistable flip-flop comprising first and second cross-coupled NOR gates; wherein said first output is connected to one input of said first NOR gate and wherein said second output is connected to one input of said second NOR gate; wherein the output of said first NOR gate and the complement of the signal at said second output are applied to a first two-input NAND gate; and wherein the output of said first NAND gate is connected to the control electrode of said fifth transistor; and wherein the output of said second NOR gate and the complement of the signal at said first output are applied to a second two input NAND gate and wherein the output of said second NAND gate is connected to the control electrode of said sixth transistor.

Claim 7

In a circuit in which first and second switching transistors driven by complementary input signals have their conduction paths connected between first and second outputs, respectively, and a first power terminal, and in which relatively high impedance loads are connected between the outputs and a second power terminal, whereby the signals at said outputs are unsymmetrical going from a second level, approximately equal to the voltage at said second power terminal, to a first level, approximately equal to the voltage at said first power terminal, much faster than from said first level to said second level, means for rendering the signal at said first and second outputs more symmetrical, comprising: first and second normally non-conducting load transistors, each load transistor having a conduction path and a control electrode, and the load transistors when turned-on exhibiting a relatively low impedance along their conduction paths; means connecting the conduction path of said first load transistor between said first output and said second power terminal, means connecting the conduction path of said second load transistor between said second output and said second power terminal; and means, coupled between said first and second outputs and the control electrodes of said first and second load transistors, responsive to the signal at said first output making a transition from said second level to said first level for turning-on said second load transistor for quickly charging said second output from said first level to said second level, and responsive to the signal at said second output being charged to said second level and the signal at said first output being at said first level for turning-off said second load transistor.

Claim 8

In a circuit in which first and second switching transistors driven by complementary input signals have their conduction paths connected between first and second outputs, respectively, and a first power terminal, and in which relatively high impedance loads are connected between the outputs and a second power terminal, whereby the signals at said outputs are unsymmetrical going from a second level, approximately equal to the voltage at said second power terminal, to a first level, approximately equal to the voltage at said first power terminal, much faster than from said first level to said second level, means for rendering the signal at said first and second outputs more symmetrical, comprising: first and second normally non-conducting load transistors, each load transistor having a conduction path and a control electrode, and the load transistors when turned-on exhibiting a relatively low impedance along their conduction paths; means connecting the conduction path of said first load transistor between said first output and said second power terminal, means connecting the conduction path of said second load transistor between said second output and said second power terminal; and means, coupled between said first and second outputs and the control electrodes of said first and second load transistors, responsive to the signal at said first output making a transition from said second level to said first level for turning-on said second load transistor for quickly charging said second output from said first level to said second level, and responsive to the signal at said second output being charged to said second level and the signal at said first output being at said first level for turning-off said second load transistor.

Claim 9

In a circuit in which first and second switching transistors driven by complementary input signals have their conduction paths connected between first and second outputs, respectively, and a first power terminal, and in which relatively high impedance loads are connected between the outputs and a second power terminal, whereby the signals at said outputs are unsymmetrical going from a second voltage level, approximately equal to the voltage at said second power terminal, to a first voltage level, approximately equal to the voltage at said first power terminal, much faster than from said first level to said second level, means for rendering the signal at said first and second outputs more symmetrical, comprising: first and second normally non-conducting load transistors, each load transistor having a conduction path and a control electrode, and the load transistors when turned-on exhibiting a relatively low impedance along their conduction paths; means connecting the conduction path of said first load transistor between said first output and said second power terminal; means connecting the conduction path of said second load transistor between said second output and said second power terminal; and means, coupled between said first and second outputs and the control electrodes of said first and second load transistors, responsive to the signal at one of said first and second outputs making a transition from said second level to said first level for turning-on the load transistor connected to the other one of said first and second outputs and quickly charging said other output from said first level towards the level at said second power terminal, and responsive to the signal at said other output being charged to approximately the level at said second power terminal and the signal at said one output being approximately equal to the level at said first power terminal for turning-off said load transistor connected to the other one of said first and second outputs.

Claim 10

In a circuit in which first and second switching transistors driven by complementary input signals have their conduction paths connected between first and second outputs, respectively, and a first power terminal, and in which relatively high impedance loads are connected between the outputs and a second power terminal, whereby the signals at said outputs are unsymmetrical going from a second voltage level, approximately equal to the voltage at said second power terminal, to a first voltage level, approximately equal to the voltage at said first power terminal, much faster than from said first level to said second level, means for rendering the signal at said first and second outputs more symmetrical, comprising: first and second normally non-conducting load transistors, each load transistor having a conduction path and a control electrode, and the load transistors when turned-on exhibiting a relatively low impedance along their conduction paths; means connecting the conduction path of said first load transistor between said first output and said second power terminal; means connecting the conduction path of said second load transistor between said second output and said second power terminal; and means, coupled between said first and second outputs and the control electrodes of said first and second load transistors, responsive to the signal at one of said first and second outputs making a transition from said second level to said first level for turning-on the load transistor connected to the other one of said first and second outputs and quickly charging said other output from said first level towards the level at said second power terminal, and responsive to the signal at said other output being charged to approximately the level at said second power terminal and the signal at said one output being approximately equal to the level at said first power terminal for turning-off said load transistor connected to the other one of said first and second outputs.