Electronic watch

Claim 2

In an electronic time keeping system including a liquid crystal display having at least one pair of energizing electrodes for receiving a pair of relatively high voltages of the same frequency which are in phase or out of phase, a system for controlling the relative phase of said pair of relatively high voltage signals in response to a relatively low voltage control signal from a source, said system comprising: a source for providing a pair of periodic relatively high voltage signals of opposite phase; a level converter adapted to be coupled to said source of low voltage control signal for converting said low voltage control signal to a high voltage control signal; a transfer gate having a pair of transfer inputs each coupled to a different one of said pair of periodic relatively high voltage signals and a control portion coupled to said level converter for transmitting a first one of said pair of periodic relatively high voltage signals to the output of said transfer gate in the absence of said control signal and for transmitting the other one of said pair of periodic relatively high voltage signals to said output when said control signal is present; and means for applying one of said pair of relatively high voltage signals to one electrode of said display and for applying said output to the other of said electrodes of said display.

Claim 3

The apparatus of claim 1 wherein said level converter comprises a bi-stable circuit switchable between opposite states in response to a change in said low voltage control signal.

Claim 4

The apparatus of claim 2 wherein said bi-stable circuit includes a control input adapted to be coupled to said relatively low voltage control signal; first and second transfer inputs adapted to be coupled to ground potential and a relatively high reference voltage, respectively: first and second transfer outputs normally coupled to said first and second transfer inputs, respectively; and means for coupling said first and second transfer outputs to said second and first transfer inputs, respectively, in response to the appearance of said relatively low voltage control signal at said control input.

Claim 5

The apparatus of claim 3 wherein said bi-stable circuit comprises a first and second pair of transistors of a first conductivity type, each of said pair coupled source-to-source and drain-to-drain the gate of a first transistor of one of said pairs coupled to said control input; an inverter having an input coupled to said control input and output, the gate of the first transistor of the other one of said pairs coupled to said inverter output, the common source of each of said pair coupled to said first transfer input, the gates of a second transistor of each of said pair coupled to the common drain of the other said pair, each one of said common drains coupled to first and second transfer outputs, the common drain terminal of each said pair coupled to the drain of a different one of a pair of opposite conductivity type transistors, the gate of each one of said opposite conductivity type transistors coupled to the common drain terminal of the other one of said pair of transistors, the source terminal of each of said opposite conductivity type transistors coupled to the drain of a different one of a second pair of opposite conductivity type transistors connected source-to-source, the source of each of the last named transistors comprising said second transfer input, the gate of each of said last named transistors adapted to be coupled to a bias voltage for rendering said last named transistors conductive.

Claim 6

The apparatus of claim 1, wherein said source of periodic relatively high voltage signals comprises an additional level converter adapted to be coupled to a source of periodic relatively low voltage reference signals for converting said low voltage reference signals to periodic relatively high voltage reference signals.

Claim 7

The apparatus of claim 5 wherein said additional level converter comprises a bi-stable circuit switchable between opposite states in response to a change in said low voltage reference signals.

Claim 8

The apparatus of claim 6, wherein said bi-stable circuit includes a control input adapted to be coupled to said relatively low voltage reference signals, first and second transfer inputs adapted to be coupled to ground potential and a relatively high voltage, respectively, first and second transfer outputs, and means for coupling said first and second outputs to alternate ones of said first and second transfer inputs in response to said reference signals at said control input so that the output signals on said first and second transfer outputs are oppositely phased.

Claim 9

The apparatus of claim 7 wherein said bi-stable circuit comprises a first and second pair of transistors of a first conductivity type, each of said pair coupled source-to-source and drain-to-drain, the gate of a first transistor of one of said pairs coupled to said control input, an inverter having an input coupled to said control input and an output, the gate of the first transistor of the other one of said pairs coupled to said inverter output, the common source of each said pair coupled to said first transfer input, the gate of a second transistor of each of said pair coupled to the common drain of the other said pair, each one of said common drains coupled to a different one of said first and second transfer outputs, the common drain terminal of each of said pair coupled to the drain of a different one of a pair of opposite conductivity type transistors, the gate of each one of said opposite conductivity type transistors coupled to the common drain terminal of the other one of said pair of transistors, a source terminal of each of said opposite conductivity type transistors coupled to the drain of a different one of a second pair of opposite conductivity type transistors connected source-to-source, the source of each of the last named transistors comprising said second transfer input, the gate of each said last named transistors adapted to be coupled to a bias voltage for rendering said last named transistors conductive.

Claim 10

The apparatus of claim 1 wherein said transfer gate comprises first and second pairs of complementary transistors, each pair comprising two opposite conductivity type transistors connected in parallel in source-drain fashion, the gate of each transistor of one pair being coupled to the gate of the opposite conductivity type transistor of the other pair, a first source-drain connection of each said pair comprising said transfer inputs, a second commonly coupled source-drain connection of each said pair comprising said transfer output, and the commonly connected gates comprising said control portion.