Process for manufacturing a buried gate field effect transistor

Claim 1

A process for manufacturing a buried gate field effect transistor, comprising, in the order mentioned, the steps of: (a) providing a structure including a semi-insulative substrate, an undoped gallium arsenide layer formed on the semi-insulative layer, a GaAlAs layer formed on the undoped gallium arsenide layer, and an undoped semiconductor layer formed on the GaAlAs layer, a first impurity region acting as a source region being formed in the undoped gallium arsenide layer, a second impurity region acting as a drain region being formed in the undoped gallium arsenide layer, and a channel layer being provided between the first and second impurity regions; (b) forming a V-shaped groove in a portion of the undoped semiconductor layer above the channel layer in the undoped gallium arsenide layer, by etching the undoped semiconductor layer with an etching solution which has a high selectivity toward the crystal face of the undoped semiconductor layer; (c) vapor-depositing a metal likely to form an alloy type of Schottky junction with the undoped semiconductor layer, on the inner wall surfaces of the V-shaped groove; and (d) heating the resultant structure until the bottom end of the V-shaped groove enters the GaAlAs layer, and the channel layer attains a prescribed threshold voltage to form an alloy-type Schottky junction between the compound semiconductor and the metal.