Patent US4489339A successfully refreshed from Google Patents.
US4489339A
Expired / Lapsed
US
⏱️ 0.0 years remaining
SOS MOSFET With self-aligned channel contact
Assignee: Toshiba Corp
•
Filing: 1983-11-14
•
Granted: 1984-12-18
•
Expires: 2003-11-14
Abstract
Abstract A MOS type semiconductor device effectively supplying potential to a substrate region under the channel forming region of the MOS transistor on an insulating substrate. The potential is supplied to the one conductivity type substrate region under the channel forming region which is provided on an insulating substrate and has an extended portion extending in the channel length direction, through a substrate potential take-out region of one conductivity type connecting to the extended substrate. A gate electrode with an extended gate portion is formed on the substrate region through a gate insulating film, so as to cover the substrate region.
Inventors
- 👤 Yukimasa Uchida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:19
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/6704; H10D30/6708; H10D86/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
234 words
A MOS type semiconductor device comprising: an insulating substrate; a substrate region of one conductivity type provided on said insulating substrate, said substrate region positioned under a channel region, and said substrate region having an extended substrate portion extending in the channel length, which is the direction of current flow, away from said channel region; a source region of an opposite conductivity type which is provided in said insulating substrate, contacting one side surface of said substrate region under said channel region; a drain region of the opposite conductivity type which is provided on said insulating substrate, contacting the other side surface of said substrate region under said channel region, the pair of said source and drain regions being separately formed sandwiching said substrate region under the channel region and said extended substrate portion extending to one of said source and drain regions; a gate insulating film provided on said substrate region; a gate electrode provided on said gate insulating film so as to cover said substrate region, said gate electrode having an extended gate portion corresponding to said extended substrate portion of said substrate region; and a substrate potential takeout region of one conductivity type which is provided on said insulating substrate and is connected to said extended substrate portion of said substrate region, whereby potential may be applied to said substrate region under the channel region through said substrate potential take-out region.
Claim 2
Dependent Claim
234 words
A MOS type semiconductor device comprising: an insulating substrate; a substrate region of one conductivity type provided on said insulating substrate, said substrate region positioned under a channel region, and said substrate region having an extended substrate portion extending in the channel length, which is the direction of current flow, away from said channel region; a source region of an opposite conductivity type which is provided in said insulating substrate, contacting one side surface of said substrate region under said channel region; a drain region of the opposite conductivity type which is provided on said insulating substrate, contacting the other side surface of said substrate region under said channel region, the pair of said source and drain regions being separately formed sandwiching said substrate region under the channel region and said extended substrate portion extending to one of said source and drain regions; a gate insulating film provided on said substrate region; a gate electrode provided on said gate insulating film so as to cover said substrate region, said gate electrode having an extended gate portion corresponding to said extended substrate portion of said substrate region; and a substrate potential takeout region of one conductivity type which is provided on said insulating substrate and is connected to said extended substrate portion of said substrate region, whereby potential may be applied to said substrate region under the channel region through said substrate potential take-out region.
Claim 3
Dependent Claim
47 words
The MOS type semiconductor device according to claim 1, wherein said substrate region has a plurality of extended substrate portions extending in the channel length direction, and said gate electrode has a plurality of extended gate portions corresponding to said extended substrate portions of said substrate region.
Claim 4
Dependent Claim
38 words
The MOS type semiconductor device according to claim 2, wherein said substrate potential take-out region is commonly connected to the plurality of said extended substrate portions to supply potential to said substrate region under the channel forming region.
Claim 5
Dependent Claim
24 words
The MOS type semiconductor device according to any one of claims 1 to 3, wherein said extended substrate portion extends toward said source region.
Claim 6
Dependent Claim
25 words
The MOS type semiconductor device according to claim 4, wherein an electrode is formed ranging over said substrate potential take-out region and said source region.
Claim 7
Dependent Claim
40 words
The MOS type semiconductor device according to claim 1, wherein said substrate region is formed in a closed shape, within which said source region or said drain region is present, and has said extended substrate portion at a part thereof.
Claim 8
Dependent Claim
22 words
The MOS type semiconductor device according to claim 6, wherein said substrate region under the channel forming region is circular in shape.
Claim 9
Dependent Claim
21 words
The MOS type semiconductor device according to claim 6 or 7, wherein said extended substrate portion extends toward said source region.
Claim 10
Dependent Claim
26 words
The MOS type semiconductor device according to claim 8, wherein a contact hole is formed ranging over said substrate potential take-out region and said source region.
References Cited (Backward Citations)
US3786319A
Cited
US3586930A
Cited
DE2445985A1
Cited
US4025940A
Cited
DE2637479A1
Cited
US4053916A
Cited
GB1561903A
Cited
US4053916B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-18 | 1988-06-18 | 1988-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-18 | 1992-06-18 | 1992-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-18 | 1996-06-18 | 1996-12-18 | $7700.00 | Window Closed / Lapsed |