US4471523A
Expired / Lapsed
US
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Self-aligned field implant for oxide-isolated CMOS FET
Assignee: International Business Machines Corp
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Filing: 1983-05-02
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Granted: 1984-09-18
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Expires: 2003-05-02
Abstract
Abstract A process for making an integrated structure comprised of complementary MOS devices is described, where electrical isolation is provided by recessed field oxide regions and by field isolation implant regions. Starting with a single conductivity type semiconductor layer, such as P- type silicon, a first masking step is used to produce an N- type well therein. After this, a layer of silicon or silicide is formed through the same mask. In a second masking step, openings are made for the field isolation implant regions. The edge of the silicon or silicide layer determines the edge of the field isolation implant, which is therefore self-aligned to the edge of the well. This same mask is later used to determine the locations of the recessed oxide isolation regions. Subsequent masking steps are used to form polysilicon gate electrodes, source and drain regions of the active devices, contact holes and contact metal and interconnects. A high density structure is provided without an extra masking step, and the conductivity levels of the well and the field isolation implants can be separately established. No additional masking steps are required for adjusting the threshold voltages of the P and N channel devices.
Inventors
- 👤 Genda J. Hu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:05
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/13; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/40; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
259 words
A method for forming an integrated CMOS structure having P and N channel active devices in a single semiconductor layer of a first conductivity type, wherein electrical isolation is provided by recessed field oxide regions located between said devices and by field isolation implant regions located under some of said field oxide regions, comprising the steps of: forming a well of opposite conductivity type in said semiconductor layer by ion implantation through a first mask, depositing a masking layer through said first mask onto a substrate including said semiconductor layer, removing said first mask, forming a second mask over said masking layer and said substrate, said second mask having first openings therein through which said field isolation implant regions and said recessed field oxide regions are to be formed said first openings exposing an edge of said masking layer, and second openings therein for determining the locations in said semiconductor layer where said recessed field oxide regions will also be formed, forming said field isolation implant regions in said semiconductor layer by ion implantation through said first openings, said field isolation regions having an opposite conductivity type than the conductivity type of said well, the edge of said masking layer determining the edge of said field isolation regions whereby said field isolation regions are self-aligned to the edge of said well, removing those portions of said masking layer located in said second openings in said second mask, forming said recessed field oxide regions in said semiconductor layer through said openings, and forming said active devices in said semiconductor layer.
Claim 2
Independent Claim
259 words
A method for forming an integrated CMOS structure having P and N channel active devices in a single semiconductor layer of a first conductivity type, wherein electrical isolation is provided by recessed field oxide regions located between said devices and by field isolation implant regions located under some of said field oxide regions, comprising the steps of: forming a well of opposite conductivity type in said semiconductor layer by ion implantation through a first mask, depositing a masking layer through said first mask onto a substrate including said semiconductor layer, removing said first mask, forming a second mask over said masking layer and said substrate, said second mask having first openings therein through which said field isolation implant regions and said recessed field oxide regions are to be formed said first openings exposing an edge of said masking layer, and second openings therein for determining the locations in said semiconductor layer where said recessed field oxide regions will also be formed, forming said field isolation implant regions in said semiconductor layer by ion implantation through said first openings, said field isolation regions having an opposite conductivity type than the conductivity type of said well, the edge of said masking layer determining the edge of said field isolation regions whereby said field isolation regions are self-aligned to the edge of said well, removing those portions of said masking layer located in said second openings in said second mask, forming said recessed field oxide regions in said semiconductor layer through said openings, and forming said active devices in said semiconductor layer.
Claim 3
Dependent Claim
25 words
The method of claim 1, where said field oxide regions outside said well are located over said field isolation implant regions and in contact therewith.
Claim 4
Dependent Claim
24 words
The method of claim 2, where the doping level of said field isolation implant regions is independent of the doping level of said well.
Claim 5
Dependent Claim
39 words
The method of claim 3, where said semiconductor layer is a layer of silicon, said masking layer is selected from the group consisting of silicon and metal silicides, and said active devices include gate electrodes comprised of doped polysilicon.
Claim 6
Dependent Claim
44 words
The method of claim 1, including the additional step of adjusting the threshold voltages of said active devices by ion implantation of said semiconductor layer using said remaining portions of said masking layer has a mask during said implantation to adjust the threshold voltages.
Claim 7
Dependent Claim
53 words
The method of claim 5, including the additional steps of removing said remaining portions of said masking layer and further adjusting the threshold voltages of said active devices by ion implantation of said semiconductor layer using said recessed field oxide regions as a mask during said implantation to further adjust the threshold voltages.
Claim 8
Dependent Claim
52 words
The method of claim 1, including the further steps of removing said remaining portions of said masking layer and adjusting the threshold voltages of said active devices by ion implantation of said semiconductor layer using said recessed field oxide regions as a mask during said ion implantation to adjust said threshold voltages.
Claim 9
Dependent Claim
14 words
The method of claim 1, where said masking layer is a layer of silicon.
Claim 10
Dependent Claim
15 words
The method of claim 1, where said masking layer is a layer of metal silicide.
Claim 11
Dependent Claim
17 words
The method of claim 1, where said second mask is patterned prior to patterning said first mask.
Claim 12
Dependent Claim
156 words
In a process where complementary first and second sets of active devices are to be fabricated in an integrated circuit in a single semiconductor layer, the steps including forming in said semiconductor layer a well having a conductivity type opposite to that of said semiconductor layer, said well being formed in a portion of said semiconductor layer defined by an opening in a first mask, forming a masking layer through said opening in said first mask, forming a buried region of opposite conductivity type to the conductivity type of said well outside said well and self-aligned to an edge of said well using the edge of said masking layer as a mask in the formation of said buried region, patterning said masking layer to provide openings therein, and forming recessed oxide regions over said buried region and in said well using said openings to define the locations where said recessed oxide regions are to be formed.
Claim 13
Dependent Claim
156 words
In a process where complementary first and second sets of active devices are to be fabricated in an integrated circuit in a single semiconductor layer, the steps including forming in said semiconductor layer a well having a conductivity type opposite to that of said semiconductor layer, said well being formed in a portion of said semiconductor layer defined by an opening in a first mask, forming a masking layer through said opening in said first mask, forming a buried region of opposite conductivity type to the conductivity type of said well outside said well and self-aligned to an edge of said well using the edge of said masking layer as a mask in the formation of said buried region, patterning said masking layer to provide openings therein, and forming recessed oxide regions over said buried region and in said well using said openings to define the locations where said recessed oxide regions are to be formed.
Claim 14
Dependent Claim
17 words
The method of claim 11, wherein said well and said buried region are formed by ion implantation.
Claim 15
Dependent Claim
31 words
The method of claim 11, where said semiconductor layer is a layer of silicon and said masking layer is a layer selected from the group consisting of silicon and metal silicides.
Claim 16
Dependent Claim
22 words
The method of claim 13, where the conductivity level of said buried regions is independent of the conductivity level of said well.
Claim 17
Dependent Claim
40 words
The method of claim 11, including the further step of ion implanting the surface of said semiconductor layer to adjust the threshold voltages of said active devices, said ion implanting being done using said recessed oxide regions as a mask.
Claim 18
Dependent Claim
36 words
The method of claim 11, including the additional step of adjusting the threshold voltage of said active devices by ion implantation of said semiconductor layer using said masking layer as a mask during said ion implantation.
Claim 19
Independent Claim
188 words
A method for forming two ion implanted regions in a layer of semiconductor material where said ion implanted regions are self-aligned to one another using two masking steps without critical alignment, comprising the steps of: forming a first masking level over said semiconductor layer, said masking level including at least one opening therein, ion implanting said semiconductor layer through said opening to produce a first ion implanted region in said semiconductor layer, depositing a masking layer through said opening and onto a substrate including said semiconductor layer, forming a second masking level over said semiconductor and over said masking layer, said second masking level having an opening therein which exposes a portion of said masking layer including an edge thereof, the formation of openings in said second masking level being noncritical in alignment and, ion implanting said semiconductor layer through said opening in said second masking level to produce a second ion implanted region in said semiconductor layer, said second implanted region having an edge determined by said edge of said masking layer, whereby said first and second ion implanted regions have their edges self-aligned with one another.
Claim 20
Independent Claim
188 words
A method for forming two ion implanted regions in a layer of semiconductor material where said ion implanted regions are self-aligned to one another using two masking steps without critical alignment, comprising the steps of: forming a first masking level over said semiconductor layer, said masking level including at least one opening therein, ion implanting said semiconductor layer through said opening to produce a first ion implanted region in said semiconductor layer, depositing a masking layer through said opening and onto a substrate including said semiconductor layer, forming a second masking level over said semiconductor and over said masking layer, said second masking level having an opening therein which exposes a portion of said masking layer including an edge thereof, the formation of openings in said second masking level being noncritical in alignment and, ion implanting said semiconductor layer through said opening in said second masking level to produce a second ion implanted region in said semiconductor layer, said second implanted region having an edge determined by said edge of said masking layer, whereby said first and second ion implanted regions have their edges self-aligned with one another.
Claim 21
Dependent Claim
38 words
The method of claim 17, where said semiconductor layer is silicon, said first and second masking levels are comprised of patterned resist levels, and said masking layer is selected from the group consisting of silicon and metal silicides.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-18 | 1988-03-19 | 1988-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-18 | 1992-03-19 | 1992-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-18 | 1996-03-19 | 1996-09-18 | $7700.00 | Window Closed / Lapsed |