Thyristor with a multi-layer semiconductor body with a pnpn layer sequence and a method for its manufacture with a {111} lateral edge bevelling

Claim 2

A thyristor having a multi-layer semiconductor body with pnpn layer sequence which exhibits two boundary surfaces that lie essentially parallel to the pn-junctions between the individual layers, wherein said boundary surfaces exhibit a {100} direction orientation, are rectangularly configured, and have lateral limits which extend parallel to a {110} direction orientation; and wherein a plurality of {111} direction oriented pairs of lateral surfaces are provided which each proceeds from mutually corresponding limits of both said boundary surfaces and meets in a plane situated between said boundary surfaces and parallel thereto, in which plane said semiconductor body has a rectangular, minimum cross-sectional surface lying parallel to said boundary surfaces.

Claim 3

A method for manufacturing a thyristor of claim 1, wherein a monocrystalline, wafer-shaped multi-layer semiconductor body with a pnpn layer sequence and with two mutually opposite, {100} direction oriented boundary surfaces extending essentially parallel to the pn-junctions between the individual layers is employed, said boundary surfaces being each covered with a masking layer comprising the steps of cutting out of a wafer-shaped multi-layer semiconductor body a multi-layer semiconductor body of a thyristor, said cutting out being conducted along a plurality of prechosen parting surfaces, whereby each of the parting surfaces extends through a parting line which lies in one of said {100} direction oriented boundary surfaces preformed in said wafer-shaped multi-layer semiconductor body and is oriented parallel to a {110} direction orientation, subjecting the multi-layer semiconductor body of such thyristor to an etching procedure in the area of such parting surfaces with an anisotropically effective etching agent, whereby a plurality of V-shaped troughs are etched thereinto whose respective individual wall portions consist of surfaces that are {111} direction oriented and removing said masking layers.

Claim 4

The method of claim 2, wherein said wafer-shaped multi-layer semiconductor body consists of silicon.

Claim 5

The method of claim 3, wherein said masking layers consist of Si 3 N 4 .

Claim 6

The method of claim 3, wherein said masking layers consist of SiO 2 .

Claim 7

The method of claim 2, wherein a solution of potassium hydroxide is employed as said etching agent.

Claim 8

The method of claim 2, wherein such separation of said thyristor semiconductor body from said wafer-shaped multi-layer semiconductor body is achieved by sawing.

Claim 9

The method of claim 2, wherein such separation of said thyristor semiconductor body from said wafer-shaped multi-layer semiconductor body is achieved by irradiation with a laser beam.