High speed and current gain insulated gate field effect transistors

Claim 2

A high speed, high current gain insulated gate field effect transistor comprising: a body region of semiconductor material having a first conductivity type; a continuous source region and a continuous drain region each having a second conductivity type opposite said first conductivity type spaced apart in the surface of said body region defining a channel region therebetween; a gate over said channel region between said source and drain regions and separated from said body by an insulative layer; a source conductor in contact with said source region at a plurality of distinct positions adjacent said channel region; a drain conductor in contact with said drain region at a plurality of distinct positions across said channel from corresponding source distinct positions; said source conductor and said drain conductor form a plurality of electrically parallel insulated gate transistors having a common source region, common drain region and common gate.

Claim 3

The insulated gate field effect transistor according to claim 1 including gate conductor means in contact with both ends of said gate for reducing the series resistance of said gate.

Claim 4

The insulated gate field effect transistor according to claim 1 wherein said drain region has a substantially smaller surface area than said source region.

Claim 5

The insulated gate field effect transistor according to claim 1 wherein said source region and said drain region are rectangular regions having a substantially greater length than width, the regions are spaced widthwise, and have equal length.

Claim 6

The insulated gate field effect transistor according to claim 1 wherein said gate is a polycrystalline semiconductor material.

Claim 7

The insulated gate field effect transistor according to claim 1 wherein said gate is a metallic material.

Claim 8

An insulated gate field effect transistor comprising: a body of semiconductor materials of a first conductivity type; a pair of spaced drain regions of a second conductivity type opposite said first conductivity type in the surface of said body; a source region of said second conductivity type in the surface of said body between and spaced from said drain regions; a pair of gates each over the body region between said source region and a respective drain region and separated from said body by an insulative layer; a drain conductor having a base portion and a pair of parallel fingers extending from said base portion, each finger being over a respective drain region and making contact therewith; a source conductor having a base portion and a finger portion extending from said base portion parallel to said drain finger portions, said source finger portion being over said source region and making contact therewith; said drain and source finger portions being interdigitated; a gate conductor extending about and around said source and drain finger portions without traversing said source and drain conductors; said gate conductor contacting both ends of each of said pair of gates to reduce the series resistance of said gates.

Claim 9

An insulated gate field effect transistor comprising: a body of semiconductor materials of a first conductivity type; a pair of spaced drain regions of a second conductivity type opposite said first conductivity type in the surface of said body; a source region of said second conductivity type in the surface of said body between and spaced from said drain regions; a pair of gates each over the body region between said source region and a respective drain region and separated from said body by an insulative layer; a drain conductor having a base portion and a pair of parallel fingers extending from said base portion, each finger being over a respective drain region and making contact therewith; a source conductor having a base portion and a finger portion extending from said base portion parallel to said drain finger portions, said source finger portion being over said source region and making contact therewith; said drain and source finger portions being interdigitated; a gate conductor extending about and around said source and drain finger portions without traversing said source and drain conductors; said gate conductor contacting both ends of each of said pair of gates to reduce the series resistance of said gates.

Claim 10

The insulated gate field effect transistor according to claim 7 wherein said source conductor finger contacts said source region in a plurality of positions and each of said drain conductor fingers contacts their respective drain region in a plurality of positions corresponding to the plurality of source contact positions to form a plurality of electrically parallel connected insulated gate field effect transistors.

Claim 11

The insulated gate field effect transistor according to claim 7 wherein said source and drain regions are generally rectangular, have substantially the same length and being spaced widthwise, and said source region has a substantially greater width than said drain regions.

Claim 12

The insulated gate field effect transistor according to claim 7 wherein said gate conductor traverses said source region and said body exterior said source and drain regions without traversing said drain regions.

Claim 13

The insulated gate field effect transistor according to claim 7 wherein said pair of gates are interconnected by said gate conductor and said gates are polycrystalline semiconductor material.

Claim 14

The insulated gate field effect transistor according to claim 7 wherein said pair of gates are interconnected by said gate conductor and said gates are metallic material.

Claim 15

An insulated gate field effect transistor comprising: a body of semiconductor materials of a first conductivity type; a pair of spaced source regions of a second conductivity type opposite said first conductivity type in the surface of said body; a drain region of said second conductivity type in the surface of said body between and spaced from said source regions; a pair of gates each over the body region between said drain region and a respective source region and separated from said body by an insulative layer; a source conductor having a base portion and a pair of parallel fingers extending from said base portion, each finger being over a respective source region and making contact therewith; a drain conductor having a base portion and a finger portion extending from said base portion parallel to said source finger portions, said drain finger portion being over said drain region and making contact therewith; said drain and source finger portions being interdigitated; a gate conductor extending about and around said source and drain finger portions without traversing said source and drain conductors; said gate conductor contacting both ends of each of said pair of gates to reduce the series resistance of said gates.

Claim 16

An insulated gate field effect transistor comprising: a body of semiconductor materials of a first conductivity type; a pair of spaced source regions of a second conductivity type opposite said first conductivity type in the surface of said body; a drain region of said second conductivity type in the surface of said body between and spaced from said source regions; a pair of gates each over the body region between said drain region and a respective source region and separated from said body by an insulative layer; a source conductor having a base portion and a pair of parallel fingers extending from said base portion, each finger being over a respective source region and making contact therewith; a drain conductor having a base portion and a finger portion extending from said base portion parallel to said source finger portions, said drain finger portion being over said drain region and making contact therewith; said drain and source finger portions being interdigitated; a gate conductor extending about and around said source and drain finger portions without traversing said source and drain conductors; said gate conductor contacting both ends of each of said pair of gates to reduce the series resistance of said gates.

Claim 17

The insulated gate field effect transistor according to claim 13 wherein said drain conductor finger contacts each drain region in a plurality of positions and each of said source conductor fingers contacts their respective source region in a plurality of positions corresponding to the plurality of drain contact positions to form a plurality of electrically parallel connected insulated gate field effect transistors.

Claim 18

The insulated gate field effect transistor according to claim 13 wherein said source and drain regions are generally rectangular, have substantially the same length and being spaced widthwise, and said source regions have a substantially greater width than said drain region.

Claim 19

The insulated gate field effect transistor according to claim 13 wherein said gate conductor traverses said source regions and said body exterior said source and drain regions without traversing said drain region.

Claim 20

The insulated gate field effect transistor according to claim 13 wherein said pair of gates are interconnected by said gate conductor and said gates are polycrystalline semiconductor material.

Claim 21

The insulated gate field effect transistor according to claim 13 wherein said pair of gates are interconnected by said gate conductor and said gates are metallic material.

Claim 22

An insulated gate field effect transistor comprising: a body of semiconductor material of a first conductivity type; a plurality of source regions of a second conductivity type opposite said first conductivity type spaced in said body; a plurality of drain regions of said second conductivity type in said body spaced from and interdigitated with said source regions; a plurality of gates over the body regions between said source and drain regions and separated from said body by a layer of insulation; a plurality of source conductor fingers each over and making contact with a corresponding source region and extending from a source conductor base to connect said source regions in parallel electrically; a plurality of drain conductor fingers each over and making contact with a corresponding drain region, interdigitated with said source fingers and extending from a drain conductor base to connect said drain regions in parallel electrically; and a gate conductor traversing the area between said source and drain conductor fingers in a serpentine pattern and making contact with each gate to contact the gates in series electrically.

Claim 23

An insulated gate field effect transistor comprising: a body of semiconductor material of a first conductivity type; a plurality of source regions of a second conductivity type opposite said first conductivity type spaced in said body; a plurality of drain regions of said second conductivity type in said body spaced from and interdigitated with said source regions; a plurality of gates over the body regions between said source and drain regions and separated from said body by a layer of insulation; a plurality of source conductor fingers each over and making contact with a corresponding source region and extending from a source conductor base to connect said source regions in parallel electrically; a plurality of drain conductor fingers each over and making contact with a corresponding drain region, interdigitated with said source fingers and extending from a drain conductor base to connect said drain regions in parallel electrically; and a gate conductor traversing the area between said source and drain conductor fingers in a serpentine pattern and making contact with each gate to contact the gates in series electrically.

Claim 24

The insulated gate field effect transistor according to claim 19 wherein said source conductor fingers contact their respective source region in a plurality of positions and each of said drain conductor fingers contact their respective drain region in a plurality of positions corresponding to the plurality of source contact positions to form a plurality of electrically parallel connected insulated gate field effect transistors.

Claim 25

The insulated gate field effect transistor according to claim 19 wherein said source and drain regions are generally rectangular, have substantially the same length and being spaced widthwise, and said source regions have a substantially greater width than said drain regions.

Claim 26

The insulated gate field effect transistor according to claim 19 wherein said gate conductor traverses said source regions and said body exterior said source and drain regions without traversing said drain regions.

Claim 27

The insulated gate field effect transistor according to claim 22 wherein said gates include end portions extending beyond said source and drain regions to over said body, said gate conductor contacts both end portions of each gate.

Claim 28

The insulated gate field effect transistor according to claim 19 wherein said gate is polycrystalline semiconductor material.

Claim 29

The insulated gate field effect transistor according to claim 19 wherein said gate is metallic material.