Patent US4458162A successfully refreshed from Google Patents.
US4458162A
Expired / Lapsed
US
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TTL Logic gate
Assignee: International Business Machines Corp
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Filing: 1981-07-10
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Granted: 1984-07-03
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Expires: 2001-07-10
Abstract
Abstract A Transistor-Transistor Logic (TTL) gate is disclosed wherein a different amount of base current is applied to the inverter transistor than is applied to the base of the output transistor. In one embodiment, a current mirror circuit controls the amount of base current flowing between the input transistor collector terminal and the base terminal of the inverter transistor to an amount less than that flowing between the input transistor collector terminal and the base terminal of the output transistor. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.
Inventors
- 👤 Paul M. Solomon
- 👤 Siegfried K. Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K19/0008; H03K19/001; H03K19/01; H03K19/013
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
187 words
A logic gate comprising: an input transistor having a base terminal, a collector terminal and at least one emitter terminal connected to an input node, said base terminal being connected to a source of potential, an output transistor having an emitter terminal connected to ground, a collector terminal connected to an output node and a base terminal connected to said collector terminal of said input transistor, an inverter transistor having an emitter terminal, a base terminal connected to said collector terminal of said input transistor and a collector terminal connected to said source of potential, a pull-up transistor having an emitter terminal connected to said output node, a base terminal connected to the collector terminal of said inverter transistor and a collector terminal connected to said source of potential, and, a current mirror circuit electrically connected to said emitter terminal of said inverter transistor for controlling the amount of base current flowing between said input transistor collector terminal and said base terminal of said inverter transistor to an amount less than that flowing between said input transistor collector terminal and said base terminal of said output transistor.
Claim 2
Dependent Claim
187 words
A logic gate comprising: an input transistor having a base terminal, a collector terminal and at least one emitter terminal connected to an input node, said base terminal being connected to a source of potential, an output transistor having an emitter terminal connected to ground, a collector terminal connected to an output node and a base terminal connected to said collector terminal of said input transistor, an inverter transistor having an emitter terminal, a base terminal connected to said collector terminal of said input transistor and a collector terminal connected to said source of potential, a pull-up transistor having an emitter terminal connected to said output node, a base terminal connected to the collector terminal of said inverter transistor and a collector terminal connected to said source of potential, and, a current mirror circuit electrically connected to said emitter terminal of said inverter transistor for controlling the amount of base current flowing between said input transistor collector terminal and said base terminal of said inverter transistor to an amount less than that flowing between said input transistor collector terminal and said base terminal of said output transistor.
Claim 3
Dependent Claim
23 words
A logic gate according to claim 1 wherein said input transistor includes a plurality of emitters each connected to its own input node.
Claim 4
Dependent Claim
61 words
A logic gate according to claim 1 further including: a first resistor connected between the base of said input transistor and said source of potential, a second resistor connected between said source of potential and said collector of said inverter transistor and said base of said pull-up transistor, and, a diode connected between the base and collector of said output transistor.
Claim 5
Dependent Claim
85 words
A logic circuit according to claim 1 wherein said current mirror circuit includes a first transistor, the collector of which is connected to said emitter of said inverter transistor, the emitter of which is connected to ground and the base of which is connected to the base of a second transistor, the emitter and collector of said second transistor being connected to ground and to a source of DC voltage, respectively, and, an interconnection connecting said collector and said base of said second transistor together.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-03 | 1988-01-02 | 1988-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-03 | 1992-01-02 | 1992-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-03 | 1996-01-02 | 1996-07-03 | $7700.00 | Window Closed / Lapsed |