Patent US4456488A successfully refreshed from Google Patents.
US4456488A
Expired / Lapsed
US
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Method of fabricating an integrated planar transistor
Assignee: ITT Inc
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Filing: 1982-03-31
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Granted: 1984-06-26
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Expires: 2002-03-31
Abstract
Abstract A method is disclosed for fabricating a monolithic integrated planar transistor whose emitter region (1) is diffused into the base region (3) on one surface side of a semiconductor wafer (2), which base region is diffused into the collector region (4). To achieve particularly small transistor structures with high cutoff frequencies, after the diffusion of the collector region (4), the impurities of the base region (3) and those of the emitter region (1) are introduced into the surface of the collector region (4) by masked ion implantation, and the implanted ions are then activated in a single tempering process, during which the base region (3) and the emitter region (1) are formed below a protective insulating layer (5) which remains on the semiconductor surface. In the protective insulating layer, windows are formed for depositing the contacts (6, 7, 8) of the collector region (4), the base region (3), and the emitter region (1).
Inventors
- 👤 Hans-Jurgen Gahle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:21
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/21; H10P30/212; H10P30/28
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
127 words
In a method for fabricating an integrated planar transistor from a semiconductor body having a planar surface comprising the initial steps of: introducing first impurities for a collector region into said surface by masked ion implantation and a first diffusion of said first impurities in an oxidizing atmosphere, the improvement comprising the subsequent steps of: sequentially introducing into said surface second impurities of a base region and third impurities of an emitter region by sequential masked ion implantations in an oxidizing atmosphere; covering said surface with a protective insulating layer; simultaneously diffusing said second impurities in said base region and said third impurities in said emitter region by application of heat; forming openings in said protective insulating layer in predetermined locations; and depositing contacts in said openings.
Claim 2
Dependent Claim
127 words
In a method for fabricating an integrated planar transistor from a semiconductor body having a planar surface comprising the initial steps of: introducing first impurities for a collector region into said surface by masked ion implantation and a first diffusion of said first impurities in an oxidizing atmosphere, the improvement comprising the subsequent steps of: sequentially introducing into said surface second impurities of a base region and third impurities of an emitter region by sequential masked ion implantations in an oxidizing atmosphere; covering said surface with a protective insulating layer; simultaneously diffusing said second impurities in said base region and said third impurities in said emitter region by application of heat; forming openings in said protective insulating layer in predetermined locations; and depositing contacts in said openings.
Claim 3
Dependent Claim
17 words
A method in accordance with claim 1, wherein during said diffusing steps said protective layer is densified.
Claim 4
Dependent Claim
36 words
A method in accordance with claim 1, wherein said first diffusion is performed in such a slightly oxidizing atmosphere as to produce an oxide layer through which said second and third impurities may subsequentially be implanted.
Claim 5
Independent Claim
47 words
A method in accordance with claims 1 or 3 wherein said third impurity is implanted through openings of an implantation mark, said openings including an emitter region implantation opening and a frame shaped opening surrounding said emitter region implantation opening defining a frame shaped collector contact region.
Claim 6
Dependent Claim
18 words
A method in accordance with claim 1, wherein during said sequential masked ion implantation photoresist masks are used.
Claim 7
Dependent Claim
18 words
A method in accordance with claim 2, wherein during said sequential masked ion implantation photoresist masks are used.
Claim 8
Dependent Claim
18 words
A method in accordance with claim 3, wherein during said sequential masked ion implantation photoresist masks are used.
Claim 9
Dependent Claim
18 words
A method in accordance with claim 4, wherein during said sequential masked ion implantation photoresist masks are used.
Claim 10
Independent Claim
117 words
A method for fabricating an integrated planar transistor from a semiconductor body having a planar surface comprises: diffusing a first impurity into a predetermined collector region on said surface; depositing a second mask layer on said surface having an opening defining a base region on said surface within said collector region; implanting a second impurity into said base region; removing said second mask layer; depositing a third mask layer on said surface having an opening defining an emitter region on said surface within said base region; implanting a third impurity into said emitter region; removing said third mask layer; and simultaneously diffusing said second impurities in said base region and said third impurities in said emitter region.
Claim 11
Independent Claim
117 words
A method for fabricating an integrated planar transistor from a semiconductor body having a planar surface comprises: diffusing a first impurity into a predetermined collector region on said surface; depositing a second mask layer on said surface having an opening defining a base region on said surface within said collector region; implanting a second impurity into said base region; removing said second mask layer; depositing a third mask layer on said surface having an opening defining an emitter region on said surface within said base region; implanting a third impurity into said emitter region; removing said third mask layer; and simultaneously diffusing said second impurities in said base region and said third impurities in said emitter region.
Claim 12
Dependent Claim
23 words
A method in accordance with claim 9, wherein prior to said simultaneous diffusion step, a protective insulating layer is deposited on said surface.
Claim 13
Dependent Claim
27 words
A method in accordance with claim 9, wherein said second impurity implantation step is an ion implantation; and said third impurity implantation step is an ion implantation.
Claim 14
Dependent Claim
52 words
A method in accordance with claim 9, wherein said first impurity diffusing step comprises: depositing a first mask layer on said surface having an opening defining said collector region; implanting said first impurity in said collector region; and diffusing said first impurities in said collector region by a first application of heat.
Claim 15
Dependent Claim
19 words
A method in accordance with claim 9, wherein said second impurity is boron and said third impurity is arsenic.
Claim 16
Dependent Claim
59 words
A method in accordance with claim 9, wherein said second mask layer comprises a guard ring opening defining a guard ring region surrounding said collector region; during said second impurity implanting step, said second impurity is further implanted in said guard ring region; and during said simultaneous diffusing step, said second impurity is diffused in said guard ring region.
Claim 17
Dependent Claim
58 words
A method in accordance with claim 9, wherein said third mask layer comprises a collector contact opening defining a collector contact region surrounding said emitter region; during said third impurity implanting step, said third impurity is implanted in said collector contact region; and during said simultaneous diffusing step said third impurity is diffused in said collector contact region.
Claim 18
Dependent Claim
19 words
A method in accordance with claim 12, wherein said simultaneous diffusing step comprises subjecting said semiconductor body to heat.
Claim 19
Dependent Claim
23 words
A method in accordance with claim 16, wherein prior to said simultaneous diffusion step a protective insulating layer is deposited on said surface.
Claim 20
Dependent Claim
13 words
A method in accordance with claim 13, wherein said first impurity is phophorous.
Claim 21
Dependent Claim
58 words
A method in accordance with claim 14, wherein said third mask layer comprises a collector contact opening defining a collector contact region surrounding said emitter region; during said third impurity implanting step, said third impurity is implanted in said collector contact region; and during said simultaneous diffusing step, said third impurity is diffused in said collector contact system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-26 | 1987-12-26 | 1988-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-26 | 1991-12-26 | 1992-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-26 | 1995-12-26 | 1996-06-26 | $7700.00 | Window Closed / Lapsed |