← Back to Patent Explorer
US4453174A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor integrated circuit device with non-volatile semiconductor memory cells and means for relieving stress therein

Assignee: Toshiba Corp
•
Filing: 1980-05-22
•
Granted: 1984-06-05
•
Expires: 2000-05-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Disclosed is a metal oxide semiconductor integrated circuit device having an array of electrically rewritable, insulated gate type non-volatile semiconductor memory cells formed on a semiconductor substrate, read/write mode setting circuit and address designating circuits arranged corresponding to the memory cell array, those circuits being fabricated on the substrate, and a field insulating layer formed on the substrate. A cut portion is formed in the field insulating layer to surround the memory cell array.

Inventors

  • 👤 Yuichi Kawasaki
  • 👤 Sumio Tanaka
  • 👤 Hiroshi Iwahashi
  • 👤 Masamichi Asano
  • 👤 Shinichi Maekawa
  • 👤 Masazi Mito

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 18:50
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/83138

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 129 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate; (b) an array of insulated gate semiconductor memory cells formed on said substrate with said array including a peripheral circuit section, also formed on said substrate, having at least a part of a control circuit for selectively executing read/write operation of said semiconductor memory cells; (c) a field insulating layer formed on said semiconductor substrate and surrounding said array; and (d) means for blocking distortion developed during manufacturting of said device peripherally to said array from being transferred to said array of insulated gate semiconductor memory cells, wherein said means for blocking is a groove passing through said field insulating layer substantially to the surface of said substrate and substantially surrounding said array of insulated gate semiconductor memory cells.
Claim 2
Dependent Claim 129 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate; (b) an array of insulated gate semiconductor memory cells formed on said substrate with said array including a peripheral circuit section, also formed on said substrate, having at least a part of a control circuit for selectively executing read/write operation of said semiconductor memory cells; (c) a field insulating layer formed on said semiconductor substrate and surrounding said array; and (d) means for blocking distortion developed during manufacturting of said device peripherally to said array from being transferred to said array of insulated gate semiconductor memory cells, wherein said means for blocking is a groove passing through said field insulating layer substantially to the surface of said substrate and substantially surrounding said array of insulated gate semiconductor memory cells.
Claim 3
Dependent Claim 22 words
A semiconductor integrated circuit device according to claim 1, wherein said semiconductor memory cells are made of stacked-gate avalanche-injection metal oxide semiconductor.
Claim 4
Dependent Claim 40 words
A semiconductor integrated circuit device according to claim 1, further comprising a semiconductor region which is formed in the surface area of said semiconductor substrate below said groove and has a higher impurity concentration than that of said semiconductor substrate.
Claim 5
Dependent Claim 22 words
A semiconductor integrated circuit device according to claim 3, wherein said semiconductor memory cells are made of stacked-gate avalanche-injection metal oxide semiconductor.

References Cited (Backward Citations)

NL6607320A Cited
US3786318A Cited
US3696274A Cited
US3825945A Cited
US3961355A Cited
US3969747A Cited
US3978577A Cited
US4163245A Cited
US4122544A Cited
US4288807A Cited
US4247788A Cited
US4278705A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-06-05 1987-12-05 1988-06-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-06-05 1991-12-05 1992-06-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-06-05 1995-12-05 1996-06-05 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag